Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-11-13
2001-07-03
Yoo, Do (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S171000, C711S217000, C711S218000
Reexamination Certificate
active
06256718
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memories, and more specifically to protocol-based dynamic random-access memories such as Rambus dynamic RAMs
2. Description of the Related Art
Protocol-based dynamic random-access memories developed by Rambus Inc. are considered to be a representative of future technologies for personal computers because of a number of beneficial features, among which high speed performance is most attractive. In a Rambus memory system, dynamic RAMs are connected via a bus to a master device, the master device sends packets in a predetermined address format to a destination bus interface that interfaces to the associated dynamic RAM. This address format varies with the size of each RAM.
When it is desired to reconfigure the memory system, some of the memories of default size are assembled into a memory of larger size. This reconfiguration is unknown to the master device, or memory controller. When the reconfigured memory system is then initialized to update the device identifiers of the bus interfaces, discrepancies occur in address format between the memory controller and the bus interfaces. As a result, part of the identifier bits sent from the memory controller is discarded and same identifiers are assigned to different bus interfaces.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a protocol-based memory system that can uniquely assign device identifiers in an initialization process performed after the memories of default size are reconfigured without modifications on the memory controller.
According to a first aspect of the present invention, there is provided a memory system comprising a plurality of memories, a plurality of bus interfaces respectively associated with the memories, and a memory controller connected to the bus interfaces via a bus for successively transmitting request packets to the bus during an initialization phase of the memory system, each of the packets including a unique device identifier for identifying each of the bus interfaces. Each of the bus interfaces, when enabled, receives the packets of at least two successive arrivals, establishes an identifier of the bus interface using the device identifier contained in a predetermined one of the received packets by ignoring one or more of the device identifiers contained in the other packets, and enables an adjacent one of the bus interface after the bus interface has received all of said request packets.
According to a second aspect, the present invention provides a method for initializing a semiconductor memory system when memory size is increased by a factor of 2
N
, where N is an integer equal to or greater than unity, wherein the memory system comprises a memory controller and a plurality of memories and a plurality of bus interfaces respectively associated with the memories, there being a mismatch of N bits between address format of each of the bus interfaces and address format of the memory controller, the method comprising the steps of (a) enabling one of the bus interfaces and successively transmitting request packets from the memory controller to the enabled bus interface, each of the packets including a unique device identifier for identifying each of the bus interfaces, (b) receiving the packets of successive 2
N
arrivals at the enabled bus interface, (c) establishing an identifier of the enabled bus interface using the device identifier contained in a predetermined one of the received packets and ignoring the device identifier contained in other 2
N
−1 received packets, and (d) enabling an adjacent one of the bus interface, instead of the bus interface which is enabled by the step (a).
REFERENCES:
patent: 6003110 (1999-12-01), Brandt et al.
patent: 6058464 (2000-05-01), Taylor
patent: 9-293393 (1997-11-01), None
patent: 9-293015 (1997-11-01), None
McGinn & Gibb PLLC
NEC Corporation
Pham Vu A.
Yoo Do
LandOfFree
Protocol-based memory system for initializing bus interfaces... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Protocol-based memory system for initializing bus interfaces..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Protocol-based memory system for initializing bus interfaces... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2555700