Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-07-25
2004-08-24
Toatley, Jr., Gregory J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
Reexamination Certificate
active
06781804
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to components associating in the same substrate vertical diffused-type MOS power transistors (VDMOS) and logic circuits, and more specifically relates to the use of such components in circuits supplied by a battery, such as automobile circuits.
2. Discussion of the Related Art
FIG. 1
very schematically shows a portion of such a component. This component includes an N-type substrate generally formed of an N-type epitaxial layer
1
formed on an N
+
-type substrate
2
. A power transistor is formed in the right-hand portion and a logic well is formed in the left-hand portion.
The power transistor includes a set of identical cells connected to one another, such as cell
3
. Each cell includes a P-type well
4
, the central portion
5
of which is more heavily doped. An N-type ring
6
is formed in the upper portion of the well. The portion separating the external periphery of ring
6
from the external periphery of well
4
is coated with an isolated gate
8
. N-type ring
6
as well as central portion
5
of the well are coated with a metallization
9
. All gates
8
are connected to a gate terminal G and all metallizations
9
are connected to a source terminal S. The rear surface of the structure is coated with a drain metallization D. Thus, when a gate signal is applied, a current is likely to flow from terminal D to terminal S from N regions
1
and
2
to N regions
6
, via a channel formed under the insulated gates. This structure is generally used so that the drain is biased to a positive potential with respect to the source.
Elements of logic circuits are formed in one or several wells
10
. An elementary MOS transistor
11
having drain, source, and gate terminals g, d, and s has been shown in a well
10
. This is only an example of a component that could be formed in a logic well.
The voltages on the several components formed in the logic well must be applied with respect to a reference. The simplest way to provide this reference, that is, to implement a ground connection, is illustrated in FIG.
1
and corresponds to the use of a well contacting area
12
formed on a region
13
of same type (P) as the well and more heavily doped. Contact
12
may be connected directly to the ground in simple embodiments. Generally, it should be understood that, for example, high voltages VDD are applied to some drains of the MOS transistors of the logic circuit which have their sources connected to contact
12
and to the ground.
FIG. 2
shows an example of an assembly of a component of the type shown in FIG.
1
. The component is generally designated by block
20
surrounded with a frame in dotted lines. A reverse diode D
1
is illustrated in parallel between the drain and the source of MOS power transistor T and corresponds to the junction between N-type substrate
1
and P-type region
5
. Well
10
is represented by a block and it is assumed that it is connected to drain D of the MOS transistor via a diode D
2
corresponding to the junction between substrate
1
and well
10
.
In a very simple example of assembly, contact
12
of the well is grounded by a connection
21
; and the source of the power transistor is connected to the ground via a load L, the switched supply of which is desired to be performed by the power transistor. A supply source such as a battery
23
is connected between the ground and drain terminal D of power transistor T. Thus, in normal operation, diodes D
1
and D
2
are reverse biased. According to its control, transistor T will be turned on or not and no current flows from the ground (contact
12
) to the rear surface of the component (terminal D) due to the existence of reverse-biased diode D
2
.
Two incidents likely to occur in battery-powered circuits, and more specifically in automobile circuits, should however be considered.
The first incident corresponds to a biasing inversion of the battery. Diodes D
1
and D
2
are then forward biased. The current in diode D
1
is limited by the presence of load L. Thus, the current will essentially flow through diode D
2
, as indicated by arrow
24
. This current is likely to be destructive.
A second incident corresponds to a supply interruption, or battery disconnection, likely to occur when, due to vibrations or for any other reason, a lead wire of the battery breaks or operates intermittently. Then, if load L is inductive, the current will continue to flow therethrough according to the path designated by arrow
26
. It should be noted that this current will necessarily exist, load L having to be considered as a current source. In the case of the simple assembly of
FIG. 1
, this current flow raises no specific problem. The problems result from the use of known protections against battery voltage inversions, as will be seen hereafter.
A first conventional solution to solve the battery inversion problem consists of inserting a diode, biased in a direction opposite to that of diode D
2
, in series with the well. The inserting of a diode may for example be performed in the way illustrated in
FIG. 1
, by adding an N
+
-type region
15
, grounding this region
15
by a connection
17
, and suppressing the connection to ground
21
. Various solutions have been provided to optimize the operation of this diode, and to have a well referenced to the ground when the circuit is in a normal operation state. Reference will especially be made to U.S. Pat. No. 5,099,302 (Antoine Pavlin) relating to an active diode which is incorporated herein by reference. There still remains the problem that, in the case of a battery disconnection, current
26
will have to cross an avalanching diode and will dissipate a high power therein, which can cause a destruction of the component, unless a diode having a large surface is provided, which unduly increases the cost of the component.
A second conventional solution to the battery inversion problem consists of placing in series in connection
21
a resistor, a terminal of which will form the ground connection. But a new dilemma, difficult to solve, arises. Indeed, in normal operation, the resistance must be as low as possible to limit the voltage drop there across caused by the consumption of the elements of the logic circuit. Conversely, to solve the problems linked to the battery inversion case, this resistance must be as high as possible to limit the current flowing through the well.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a structure for ground connection of the logic well of a component integrating a power transistor and logic elements which does not adversely affect the normal state operation, which prevents the current flow in the logic circuit in case of a battery inversion, and which lets through the current resulting from a battery disconnection.
To achieve these and other objects, the present invention provides a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. This structure includes, in the logic well, a region of the first type of conductivity on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.
According to an embodiment of the present invention, the rectifying contact corresponds to a contact with regions of the second type of conductivity.
According to an embodiment of the present invention, the rectifying contact corresponds to a Schottky contact.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 4178619 (1979-12-01), Seiler et al.
patent: 4260910 (1981-04-01), Colman
paten
Benenson Boris
Jorgenson Lisa K.
Morris James H.
SGS-Thomson Microelectronics S.A.
Toatley , Jr. Gregory J.
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