Protection of low-k dielectric in a passivation level

Details Protection of low-k dielectric in a passivation level Protection of low-k dielectric in a passivation level

2007-03-20

2007-03-20

Norton, Nadine (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

C438S698000, C438S745000

Reexamination Certificate

active

10184336

ABSTRACT:
In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.

REFERENCES:
patent: 5172212 (1992-12-01), Baba
patent: 5668398 (1997-09-01), Havemann et al.
patent: 5918149 (1999-06-01), Besser et al.
patent: 5946601 (1999-08-01), Wong et al.
patent: 5963830 (1999-10-01), Wang et al.
patent: 6100184 (2000-08-01), Zhao et al.
patent: 6120844 (2000-09-01), Chen et al.
patent: 6204200 (2001-03-01), Shieh et al.
patent: 6228761 (2001-05-01), Ngo et al.
patent: 6281115 (2001-08-01), Chang et al.
patent: 6522005 (2003-02-01), Allman et al.
Seong Geon park, et al. “A New ALD-TiN/CoSi2 Contact Plug Process for Reliable and Low Defect Density Bit-Line Integration in Sub-Quarter Micron Giga-bit DRAM” IEEE 2002, pp. 282-284; Semiconductor R&D Center, Samsung Electronics Co. LTD., Korea.
J.T. Wetzel, et al. “Evaluation of Material Property Requirements and Performance of Ultra-Low Dielectric Constant Insulators for Inlaid Copper Metallization” IEEE 2001, pp. 4.11.-4.1.3: Int'l Sematech, Austin, TX; Texas Instruments, Dallas, TX; Motorola, Austin, TX; TSMC, Taiwan; IBM, Burlington.
M. Ben-Tzur, et al. “Integrated of Low-K Dielectrics in The Passivation Level of A1 Based Multilevel Interconnect Technology” submitted for Publication Mar. 2002, (2 pgs); Cypress Semiconductor, San Jose, CA., USA.
Wei-Jen Hsia, et al. “Flowfill Technology Low Dielectric Constant Materials” Retrieved from the internet:<URL:http//www.trikon.com [printed on Mar. 29, 2002] (4 pgs); LSI Logic, CA; Trikon Technologies Ltd.
Bruce W. McGaughy, et al. “A Simple Method for On-Chip, Sub-Femto Farad Interconnect Capacitance Measurement” IEEE vol. 18, No. 1 Jan. 1997, pp. 21-23: University of California, Berkeley, CA., USA.
Conference highlights latest data on SiLK resin, expanded Alliance membership, (3 pgs); Dec. 5, 2001; The Dow Chemical Company and Loomis Group; Midland, Michigan, USA.
Interconnect: The International Technology Roadmap For Semiconductors, pp. 1-25, 2001 Edition.

Affiliated with

Also associated with

Rating

Protection of low-k dielectric in a passivation level does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Protection of low-k dielectric in a passivation level, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Protection of low-k dielectric in a passivation level will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3805809