Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-23
2004-07-13
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S173000, C257S356000, C257S357000, C257S360000, C257S361000, C257S362000, C257S363000, C361S111000
Reexamination Certificate
active
06762460
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-324190, filed Oct. 24, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a protection circuit provided in a semiconductor circuit, and more particularly, to a protection circuit for protecting a semiconductor circuit from being broken by static electricity.
2. Description of the Related Art
Conventionally, various protection circuits for countermeasures to static electricity have been typically added to terminals of semiconductor circuits (hereinafter denoted “IC”) for obviating the ICs from breakage due to the static electricity. Recently, internal circuits tend to be increasingly broken by static electricity applied to an input terminal or an output terminal, which introduces into a power supply terminal supplied with a power supply potential Vcc or a ground terminal (or a reference terminal) supplied with a ground potential (or a reference potential).
For example, in the prior art, a protection circuit formed of MOS elements is arranged between a power supply terminal and a ground terminal for conducting a charge generated by static electricity, which has introduced into the power supply terminal, to the ground terminal.
The conventional protection circuit will be described below with reference to
FIGS. 1A
to
1
C.
FIG. 1A
is a circuit diagram illustrating the configuration of the conventional protection circuit;
FIG. 1B
is a schematic cross-sectional view of the protection circuit; and
FIG. 1C
illustrates a layout of the protection circuit on a semiconductor substrate.
As illustrated in
FIG. 1A
, this protection circuit comprises a p-channel MOS transistor (hereinafter denoted “p-MOS transistor”) P
11
, and an n-channel MOS transistor (hereinafter denoted “n-MOS transistor”) N
11
.
The p-MOS transistor P
11
has a source, a gate and a back gate connected to a power supply terminal TV which is supplied with a power supply potential Vcc. The n-MOS transistor N
11
has a drain connected to a power supply terminal TV, and a source, a gate and a back gate connected to a ground terminal TG supplied with a ground potential GND. Further, the p-MOS transistor P
11
has a drain connected to the ground terminal TG.
A general structure of the protection circuit in cross-section is as illustrated in FIG.
1
B. An n-type well
102
is formed within a p-type silicon semiconductor substrate
101
, and an element region separated by an element separation insulating film
103
is formed in the n-type well
102
. A source region (p
+
-type)
104
and a drain region (p
+
-type)
105
are formed in the n-type well
102
of the element region. A gate electrode
107
is placed on a channel between the source region
104
and the drain region
105
, with a gate insulating film (not shown) therebetween. The p-MOS transistor P
11
is formed of these components.
Also, a source region (n
+
-type)
121
and a drain region (n
+
-type)
122
are formed within the p-type semiconductor substrate
101
. A gate electrode
124
is placed on a channel between the source region
121
and the drain region
122
, with a gate insulating film (not shown) therebetween. The n-MOS transistor N
11
is formed of these components.
The power supply terminal TV is connected to the source region
104
, gate electrode
107
and n-type well
102
of the p-MOS transistor P
11
. The n-MOS transistor N
11
has the drain region
122
connected to the power supply terminal TV, and the source region
121
, gate electrode
124
and p-type semiconductor substrate
101
connected to the ground terminal TG. Also, the p-MOS transistor P
11
has the drain region
105
connected to the ground terminal TG.
The protection circuit is laid out on the semiconductor substrate as illustrated in FIG.
1
C. The source region
104
and drain region
105
, which comprise the p-MOS transistor P
11
, are separately positioned. The gate electrode
107
is arranged between the source region
104
and drain region
105
. A source contact
104
A is placed in the source region
104
, while a drain contact
105
A is placed in the drain region
105
. The distance between the drain contact
105
A and gate electrode
107
is longer than the distance between the source contact
104
A and gate electrode
107
.
On the other hand, the source region
121
and drain region
122
, which comprise the n-MOS transistor N
11
, are separately positioned. The gate electrode
124
is arranged between the source region
121
and drain region
122
. A source contact
121
A is placed in the source region
121
, while a drain contact
122
A is placed in the drain region
122
. The distance between the drain contact
122
A and gate electrode
124
is longer than the distance between the source contact
121
A and gate electrode
124
.
However, even though the foregoing protection circuit is added between the power supply terminal TV and ground terminal TG of the semiconductor circuit, internal elements within the semiconductor circuit are still broken frequently. Therefore, electrostatically broken locations are necessarily analyzed in conventional semiconductor circuits to make a different modification to each product.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a protection circuit comprises a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, a first p-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the gate, the source and the back gate are connected to the power supply terminal, a second p-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the source is connected to the drain of the first p-channel MOS transistor, the back gate is connected to the power supply terminal, and the gate and the drain are connected to the reference terminal, a first n-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the gate, the source and the back gate are connected to the reference terminal, and a second n-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the source is connected to the drain of the first n-channel NOS transistor, the back gate is connected to the reference terminal, and the gate and the drain being connected to the power supply terminal.
REFERENCES:
patent: 4044313 (1977-08-01), Wittlinger et al.
patent: 5698886 (1997-12-01), Thenoz et al.
patent: 5751525 (1998-05-01), Olney
patent: 5760630 (1998-06-01), Okamoto
patent: 6043538 (2000-03-01), Allen et al.
patent: 6054736 (2000-04-01), Shigehara et al.
patent: 6455895 (2002-09-01), Morishita
patent: 8-222643 (1996-08-01), None
patent: 9-326685 (1997-12-01), None
Sze, S.M., “Physics of Semiconductor Devices”, John Wily & Sons, Second Edition, 1981, pp. 453-456.*
Wolf, S, “Silicon Processing for the VLSI Era”, vol. 2—Process Integration, Lattice Press 1990, pp. 298-300.
Itoh Yoshimitsu
Kinugasa Masanori
Mizuta Masaru
Takiba Akira
Flynn Nathan J.
Kabushiki Kaisha Toshiba
Mondt Johannes
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