Protection circuit and method for protecting a semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S360000, C361S091500

Reexamination Certificate

active

06222236

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates, in general, to high voltage protection circuitry and, more particularly, to electrostatic discharge (ESD) protection circuits.
BACKGROUND OF THE INVENTION
It is well known that monolithic integrated circuits may become damaged by exposing their input or output terminals to large and sudden voltage transients such as electrostatic discharges. For example, a human body can accumulate enough charge to develop several thousand volts of potential, which can permanently damage an integrated circuit. When a charged object contacts the input or output terminals of the integrated circuit, the built-up electrostatic charge discharges and may force large currents into the integrated circuit. The large currents can rupture dielectric materials within the integrated circuits such as gate oxides or they may melt conductive materials such as polysilicon or aluminum interconnects, thereby irreparably damaging the integrated circuits.
Generally, integrated circuit manufacturers include high voltage protection circuits that shunt current away from input and output circuitry within integrated circuits to prevent the integrated circuits from being damaged by large voltage transients. One technique for protecting integrated circuits is to improve the energy dissipation capability of the protection circuitry. This is done by laying out the protection circuit to have larger geometries, wider metal interconnects, more and larger contacts, etc. A disadvantage of this approach is it increases the size of the integrated circuit and thus decreases the number of integrated circuits per semiconductor wafer, thereby increasing the cost of manufacturing the integrated circuits. In addition, larger geometries increase the capacitance of the Input/Output (I/O) terminals of the circuit being protected. This is undesirable for integrated circuits used in high frequency applications (e.g., applications such as cellular communications that operate between one megahertz (MHz) and two gigahertz (GHz)).
Accordingly, it would be advantageous to have a protection circuit for protecting high frequency integrated circuits from large voltage transients. It would be of further advantage for the protection circuit to occupy a small area and be compatible with standard semiconductor processes.


REFERENCES:
patent: 5578860 (1996-11-01), Costa et al.
patent: 6169312 (2001-01-01), Hiraga

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