Protection circuit against latch-up in a multiple-supply integra

Details Protection circuit against latch-up in a multiple-supply integra Protection circuit against latch-up in a multiple-supply integra

1998-02-23

2000-12-05

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257393, 257207, 257355, 257356, 257357, H01L 2976, H01L 2994, H01L 2710, H01L 31113, H01L 31119

Patent

active

061570702

ABSTRACT:
In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.

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patent: 5828119 (1998-10-01), Katsube
patent: 5920089 (1999-07-01), Kanazawa et al.
Microelectronic Circuits; Sedra and Smith; Chapter 7, sections 7.1, 7.2, 1987.

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