Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1994-05-19
1995-10-03
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257362, 257408, H01L 2906, H01L 2978
Patent
active
054554365
ABSTRACT:
The output buffer using an LDD NMOS is protected with an SCR at the output pad against electrostatic discharge (ESD). An abrupt (non-LDD) junction NMOS is used as the equivalent npn transistor in the pnpn SCR structure in a dedicated n-well. The non-LDD NMOS has a lower avalanche breakdown voltage than the LDD NMOS buffer, and triggers the SCR to turn on before the avalanche breakdown of the LDD transistor. This non-LDD NMOS lowers the trigger voltage and diverts the ESD current from flowing through the buffer to avoid damage to the buffer.
Besides the n-well for forming the protective SCR, auxiliary n+diffusions and n-wells are placed outside the n-well for to form drains of another non-LDD NMOS, which are connected to the positive power supply. These non-LDD NMOS act as npn transistor and are turned on when high voltage ESD pulses appears at the I/O pad or any power supply terminal to shunt the ESD current to ground, thus avoiding latch-up between the power supply terminals. The output buffer using an LDD NMOS is protected with an SCR at the output pad against electrostatic discharge (ESD). An abrupt (non-LDD) junction NMOS is used as the equivalent npn transistor in the pnpn SCR structure in a dedicated n-well. The non-LDD NMOS has a lower avalanche breakdown and a longer channel length than the LDD NMOS buffer, and triggers the SCR to turn on before the avalanche breakdown of the LDD transistor. This non-LDD NMOS lowers the trigger voltage and diverts the ESD current from flowing through the buffer to avoid damage to the buffer. Besides the n-well for forming the protective SCR, auxiliary n+diffusions and n-wells are placed outside the n-well to form collectors of npn transistors, which are connected to the positive power supply. These npn transistors are turned on when high voltage ESD pulses appear at the I/O pad or any power supply terminal to shunt the ESD current to ground, thus avoiding latch-up between the power supply terminals.
REFERENCES:
patent: 5182220 (1993-01-01), Ker et al.
patent: 5225702 (1993-07-01), Chatterjee
Chatterjee et al. "A Low Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", IEEE Elet. Dev. Let. vol. 12 Jan. 1991 pp. 21-22.
Industrial Technology Research Institute
Jackson Jerome
Lin H. C.
Monin, Jr. Donald L.
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