Protected programmable transistor with reduced parasitic capacit

Details Protected programmable transistor with reduced parasitic capacit Protected programmable transistor with reduced parasitic capacit

1991-05-15

1995-06-13

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257344, H01L 2968

Patent

active

054245672

ABSTRACT:
A programmable transistor includes impurity regions to reduce punch-through and soft-write phenomena. In order to provide a fast operation, the impurity regions are arranged with regard to one another so that parasitic capacitances at junctions of impurity regions of mutually opposite conductivity type are minimized. For these purposes, the transistor comprises a charge storage region over a channel region in a main semiconductor zone of a first conductivity type located between a source and a drain of a second conductivity type opposite to the first. A first impurity zone of the first conductivity type, substantially laterally contiguous with the drain, extends into the channel region and is more heavily doped than the main zone. The drain includes a heavily doped third impurity region and a lightly doped second impurity region that lies at least mainly between the third region and the zones.

REFERENCES:
patent: 4376947 (1983-03-01), Chiu et al.
patent: 4630085 (1986-12-01), Koyama
patent: 5005066 (1991-04-01), Chen
patent: 5079603 (1992-01-01), Komori et al.
Kume et al., "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure," IEDM 1987, pp. 560-563.
Yoshikawa et al., "Extended Abstracts of the 20th Conf. on Solid State Devices and Materials", Tokyo, 1988, pp. 165-168.

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