Protected erase voltage discharge transistor in a nonvolatile se

Details Protected erase voltage discharge transistor in a nonvolatile se Protected erase voltage discharge transistor in a nonvolatile se

1992-11-03

1994-05-03

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257320, 257322, H01L 2968, H01L 2702

Patent

active

053090128

ABSTRACT:
A semiconductor memory having a memory cell for storing a bit of data and a pull-down transistor for coupling the source of the memory cell to ground in order to read the memory cell. The pull-down transistor is comprised of a polysilicon gate coupled to a control means for switching the transistor ON/OFF; a drain diffusion region coupled to the source of the memory cell; and a source diffusion region coupled to ground. The source diffusion region is physically located closer to the memory cell than the drain diffusion region. Two P.sup.+ substrate taps are implemented--one on each side of the pull-down transistor. An N.sup.+ diffusion bar is coupled to V.sub.SS. The N.sup.+ diffusion bar and the adjacent P.sup.+ substrate tap are interleaved in a row and are coupled to metal layers by vias and contacts.

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