Protected address range in an electrically erasable programmable

Details Protected address range in an electrically erasable programmable Protected address range in an electrically erasable programmable

1995-11-08

1999-12-28

Follansbee, John A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711152, 711170, 712 37, G06F 1200

Patent

active

060094958

ABSTRACT:
An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

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Specifications for Keyboard Controller, Intel Corporation, Sep. 1990.

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