Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2000-08-31
2003-04-08
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S202000, C711S210000, C711S105000
Reexamination Certificate
active
06546453
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a computer system that includes one or more random access memory (“RAM”) devices for storing data. More particularly, the invention relates to a computer system with RAM devices in which multiple banks of storage can be accessed simultaneously to enhance the performance of the memory devices. Still more particularly, the present invention relates to a system for the mapping of processor addresses to memory device addresses that effectively minimizes simultaneous accesses to the same bank of memory to avoid access delays.
2. Background of the Invention
Superscalar processors achieve high performance by executing multiple instructions per clock cycle and by choosing the shortest possible clock cycle consistent with the design. On the other hand, superpipelined processor designs divide instruction execution into a large number of subtasks which can be performed quickly, and assign pipeline stages to each subtask. By overlapping the execution of many instructions within the pipeline, superpipelined processors attempt to achieve high performance.
Superscalar processors demand low main memory latency due to the number of instructions attempting concurrent execution and due to the increasing clock frequency (i.e., shortened clock cycle) employed by the processors. Many of the instructions include memory operations to fetch (“read”) and update (“write”) memory operands. The memory operands must be fetched from or conveyed to main memory, and each instruction must originally be fetched from main memory as well. Similarly, processors that are superpipelined demand low main memory latency because of the high clock frequency employed by these processors and the attempt to begin execution of a new instruction each clock cycle. It is noted that a given processor design may employ both superscalar and superpipelined techniques in an attempt to achieve the highest possible performance characteristics.
Processors are often configured into computer systems that have a relatively large and slow main memory. Typically, multiple random access memory (“RAM”) modules comprise the main memory system. The RAM modules may be Single Inline Memory Modules (“SIMM”), Double Inline Memory Modules (“DIMM”), or RAMbus™ Inline Memory Modules (“RIMM”) that incorporate a number of Random Access Memory (“RAM”) devices (see “RAMBUS Preliminary Information Direct RDRAM™”, Document DL0060 Version 1.01; “Direct Rambus™ RIMM™ Module Specification Version 1.0”, Document SL-0006-100; “Rambus® RIMM™ Module (with 128/144 Mb RDRAMs)” Document DL00084 Version 1.1, all of which are incorporated by reference herein). RAM devices may be Dynamic Random Access Memory (“DRAM”) devices, RAMbus™ DRAM (“RDRAM”) or any of a number of other types of memory storage devices. Each RAM device consists of a DRAM core section containing memory banks organized into rows and columns, with each column containing a number of bytes (in the preferred embodiment 16 bytes). A large main memory provides storage for a large number of instructions and/or a large amount of data for use by the processor, providing faster access to the instructions and/or data than may be achieved for example from disk storage. However, the access times of modem RAMs are significantly longer than the clock cycle length of modem processors. The memory access time for each set of bytes being transferred to the processor is therefore long. Accordingly, the main memory system is not a low latency system. Processor performance may suffer due to high memory latency.
Many types of RAMs employ a “page mode” which allows for memory latency to be decreased for transfers within the same “page”. Generally, as explained above, RAMs comprise memory arranged into rows and columns of storage. A first portion of the address identifying the desired data/instructions is used to select one of the rows (the “row address”), and a second portion of the address is used to select one of the columns (the “column address”). One or more bytes residing at the selected row and columns are provided as output of the RAM. Typically, the row address is provided to the RAM first, and the selected row is placed into a temporary sense amplifier buffer within the RAM. The row of data that is stored in the RAM's sense amplifier is referred to as a page. Thus, addresses having the same row address are said to be in the same page. Subsequent to the selected row being placed into the sense amplifier buffer, the column address is provided and the selected data is output from the RAM. A row/page hit occurs if the next address to access the RAM is within the same row/page stored in the sense amplifier buffer. Thus, the next access may be performed by providing the column portion of the address only, omitting the row address transmission. The next access to a different column may therefore be performed with lower latency, saving the time required for transmitting the row address because the page corresponding to the row has already been activated. The size of a row/page is dependent upon the number of columns within the row/page. The row/page stored in the sense amplifier within the RAM is referred to as an “open page”, since accesses within the open page can be performed by transmitting the column portion of the address only.
Unfortunately, the first access to a given row/page generally does not occur to an open row/page, thereby incurring a higher memory latency. Even further, the first access may experience a row/page miss. A row/page miss can occur if the sense amplifier has another particular row/page open, and the particular row/page must first be closed before opening the row/page containing the current access. A row/page miss can also occur if the sense amplifier is empty. Often, this first access is critical to maintaining performance in the processor within the computer system, as the data/instructions are immediately needed to satisfy a miss. Instruction execution may stall because of the row/page miss while the row/page containing the current access is being opened. The more often that instructions can access main memory using row/page hits, the lower the latency of memory access and the better the system performance. In a memory system containing many RAM devices and thus a large number of sense amplifier buffers, a large amount of memory can be accessed using row/page hits, resulting in an increased opportunity to maximize performance.
Software applications executing on the computer system frequently perform read or write operations that include a processor memory address mapped to a device address. The device address identifies a DRAM device, memory banks within the DRAM device, and rows and columns within each memory bank. The mapping of the processor memory address to the device address selects the DRAM device and row and column and manages memory bank conflicts. Memory bank conflicts are caused by attempts to perform a read or write to a memory bank within a DRAM device while another read or write is occurring to the same memory bank. Memory bank conflicts degrade memory system performance because memory transactions must be delayed while a previous memory transaction completes within the DRAM device. Thus, to increase system performance the mapping strategy implemented must reduce memory bank conflicts. Because memory configurations can vary widely in the number of DRAM devices present as well as the organization of the DRAM devices (i.e., number of memory banks, interface logic operation), it is highly desirable to permit a system programmer to program the mapping scheme for each particular configuration and software application to allow maximum system performance.
The mapping of processor memory addresses to device addresses for optimal performance must take into account read and write traffic patterns on main memory. One property of read/write memory traffic is referred to as locality of reference. Locality of refe
Bannon Peter J.
Bouchard Gregg A.
Braganza Michael C.
Kessler Richard E.
Steinman Maurice B.
Beim Michael F.
Choi Woo H.
Compaq Information Technologies Group L.P.
Conley & Rose, P.C.
Harris Jonathan M.
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