Prolonging a polysilicon layer in smaller memory cells to preven

Details Prolonging a polysilicon layer in smaller memory cells to preven Prolonging a polysilicon layer in smaller memory cells to preven

1997-09-08

1999-11-16

Tsai, Jey

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257380, 257350, 257533, 257904, H01L 2702

Patent

active

059863102

ABSTRACT:
This invention discloses a memory cell having a first polysilicon as a gate. The memory cell includes a three-layer structure covering the first polysilicon as gate with a plurality of via-1 openings exposing the first polysilicon as gate therein wherein the three-layer structure includes a first TEOS oxide layer covered by a silicon nitride layer which is covered by a second TEOS oxide layer. The second TEOS layer includes a resistor portion defined a plurality of trenches therein. The memory cell further includes a patterned second polysilicon layer covered the via-1 openings thus contacting the gate and a connector portion on the second TEOS layer to function as connector therefor. The second polysilicon layer further covering the resistor portion includes the plurality of trenches to function as a load resistor therein whereby the load resistor is prolonged by the trenches.

REFERENCES:
patent: 5757053 (1998-05-01), Liu
patent: 5872381 (1999-02-01), Kato et al.

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