Programming sequence for electrically programmable memory

Details Programming sequence for electrically programmable memory Programming sequence for electrically programmable memory

1980-02-04

1982-08-10

Tupper, Robert S.

Static information storage and retrieval

Read/write circuit

Signals

G11C 702

Patent

active

043441548

ABSTRACT:
An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. In a programming mode of operation, the application of high voltages to the row and column lines is controlled to prevent programming voltage from reaching a selected column until after all transistors in a row are turned on by programming voltage on a row line. This prevents unwanted programming conditions.

REFERENCES:
patent: 3846768 (1974-11-01), Krick
patent: 3851317 (1974-11-01), Kenyon
patent: 4063224 (1977-12-01), Kirschner
patent: 4151021 (1979-04-01), McElroy
patent: 4173791 (1979-11-01), Bell
patent: 4231110 (1980-10-01), Stinehelfer

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