Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-10-02
2004-06-08
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C326S041000
Reexamination Certificate
active
06748575
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to software tools used to program field programmable gate arrays (FPGAs) and other programmable logic devices.
2. Description of the Related Art
FIG. 1
shows a simplified schematic block diagram of a conventional FPGA
100
comprising a (2×2) array of programmable blocks. Each block in FPGA
100
comprises a programmable function unit (PFU)
102
and a supplemental logic and interconnect cell (SLIC)
104
. Connected to these blocks are input/output (I/O) blocks. Each I/O block comprises four programmable I/O units (PIOs) connected to a programmable switch box. For example, four PIOs
106
are connected to programmable switch box
108
, and four PIOs
110
are connected to programmable switch box
112
. In addition, FPGA
100
is configured with horizontal and vertical wiring that provide routing resources for connecting the various functional elements (e.g., PIOs, PFUs, and SLICs) within the FPGA. For example, switch box
108
is configured to be programmed to enable PIOs
106
to drive certain vertical wires
114
, while switch box
112
is configured to be programmed to enable PIOs
110
to drive certain horizontal wires
116
. In addition to switch boxes, such as switch boxes
108
and
112
, which provide programmable interconnects between two different sets of wires, FPGA
100
also has programmable placed switches
118
, each of which enables a corresponding pair of intersecting horizontal and vertical wires to be connected (e.g., vertical wires
114
and horizontal PFU wires
120
or horizontal wires
116
and vertical PFU wires
122
). FPGA
100
will typically include much more routing resources to, from, and between the various functional elements than that shown in
FIG. 1
, as well as additional programmable switches and other logic components.
In general, an FPGA is a particular type of a programmable logic device (PLD) that can be programmed by the user for any of a wide range of specific applications. In theory, an FPGA, such as FPGA
100
of
FIG. 1
, is provided with routing resources to connect (i.e., route) any pin on any component (e.g., a PFU, SLIC, or PIO) within the FPGA to any other pin on any other component within the FPGA. These connections are made by programming one or more programmable switches in the FPGA to establish a contiguous wiring path between the two pins. For example, in
FIG. 1
, PIO
106
-
1
can be connected to pin
2
of PFU
102
by (i) programming switch box
108
to connect PIO
106
-
1
to vertical wire
114
and (ii) programming placed switch
118
to connect vertical wire
114
to horizontal wire
120
, which is hard-wired to pin
2
of PFU
102
.
Special software tools have been developed for programming FPGAs. One such programming tool is the Epic™ program provided to customers of FPGAs sold by Agere Systems Inc. of Berkeley Heights, N.J. Programming tools like the Epic™ program can be used by a programmer to generate graphical displays showing representations of the current programming of the FPGA. Although these graphical representations may conform generally to the actually physical design and layout of the physical FPGA chip, in fact, they are merely representations of the functionality provided by the FPGA. As such, the appearance of functional elements and routing resources in the graphical displays generated by the programming tool need not correspond identically to those in the actual FPGA device.
In conventional software tools for programming FPGAs, different types of switches are typically supported. As described previously in the context of
FIG. 1
, an FPGA may have both programmable switch boxes, such as switch boxes
108
and
112
as well as programmable placed switches, such as placed switches
118
.
FIG. 2
shows a schematic representation of a placed switch
200
, similar to placed switch
118
of FIG.
1
. Placed switch
200
can be programmed to connect horizontal wire
202
with “intersecting” vertical wire
204
. When placed switch
200
is on, it provides a connection between wires
202
and
204
, and, when placed switch
200
is off, it does not provide such a connection. In conventional programming tools for FPGAs, in order for a horizontal wire to be connected to a vertical wire by a placed switch, the two wires must intersect one another in the graphical display of the FPGA generated by the programming tool.
FIG. 3
shows a schematic representation of a switch box
300
, similar to switch boxes
108
and
112
of FIG.
1
. In theory, switch box
300
can be implemented to programmably connect independently any of input wires
302
to any of output wires
304
. If the two input wires
302
are labeled A and B and the two output wires
304
are labeled C and D, switch box
300
can be programmed in any of the sixteen different combinations of connections listed in Table I. In conventional programming tools for FPGAs, in order for an input wire to be connected to an output wire by a switch box, the two wires must be connected to the switch box in the graphical display of the FPGA generated by the programming tool.
TABLE I
Combination #
Connections
1
None
2
A→C
3
A→D
4
B→C
5
B→D
6
A→C and B→D
7
A→D and B→C
8
A→C and A→D
9
B→C and B→D
10
A→C and B→C
11
A→D and B→D
12
A→C and A→D and B→C
13
A→C and A→D and B→D
14
A→C and B→C and B→D
15
A→D and B→C and B→D
16
A→C and A→D and B→C and B→D
FIG. 4
shows a schematic representation of a pseudo arc, another type of switch connection. A pseudo arc is the connection provided from an input wire
402
to an output wire
404
through a logic element
400
, such as a PFU or a SLIC. Typically, a pseudo arc is a conditional switch connection that depends on the logic implemented within element
400
. In conventional programming tools for FPGAs, in order for an input wire to be connected to an output wire via a pseudo arc, the two wires must be connected to the same logic element in the graphical display of the FPGA generated by the programming tool.
FIG. 5
shows an example of a graphical display generated by the Epic™ program for a particular FPGA.
FIG. 5
shows a display representing the entire FPGA in a single view. For a typical application, an FPGA such as that shown in
FIG. 5
will be programmed with a large number of connections between the various functional elements. In order to be useful to programmers, the Epic™ program enables a programmer to generate displays that selectively reveal individual wiring routes between particular functional elements, including the programming of the individual switches that provide those routes. In addition, the Epic™ program can display all possible connections from a selected switch-box pin. The Epic™ program also enables a programmer to zoom in on any selected region of the display.
FIG. 6
shows an example of a graphical display of one particular region of the FPGA shown in FIG.
5
. In particular,
FIG. 6
shows a switch box
600
having a number of input pins
602
and a number of output pins
604
. In the display of
FIG. 6
, no connections are shown between any of the input and output pins.
FIG. 7
shows an example of a graphical display of switch box
600
of
FIG. 6
displaying all of the possible switch-box connections
702
involving a particular input pin
602
. As shown in
FIG. 7
, switch box
600
can be independently programmed to provide a different switch-box connection
702
from input pin
602
to each different output pin
604
.
FIG. 8
shows an example of a graphical display of an entire route from output pin
804
of PFU
802
to input pin
810
of SLIC
812
. In particular, the entire route consists of (1) wire
806
connecting output pin
804
to input pin
602
of switch box
600
, (2) switch-box connection
702
connecting input pin
602
to output pin
604
of
Feng Wenyi
Oswald William A.
Roy Michael L.
Ting Eric
Lam Tuan T.
Lattice Semiconductor Corporation
Mendelsohn Steve
Nguyen Linh M.
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