Programming method to enable system recovery after power failure

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

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326 9, 39550017, 714 8, 714 47, H03K 19003, H03K 19173

Patent

active

060182504

ABSTRACT:
A programming method of a programmable logic device (PLD) to enable system recovery after power failure is provided. Key configuration bits controlling output enable signals of the PLD are programmed at a different time than all other configuration bits in the PLD. If those key bits are unprogrammed, the PLD behaves identically to a fully erased device. Thus, by programming the key configuration bits after all other bits are successfully programmed, any potential damage to the system is virtually eliminated. In this manner, if the main programming sequence is interrupted, the PLD will power up with partial internal activity, but no active output signals. Moreover, even if the interruption occurs during the programming of these few bits, the result is only a partial activation of output signals which is significantly better than the activation of output signals with incorrect functions.

REFERENCES:
patent: 5737235 (1998-04-01), Kean et al.
patent: 5869979 (1999-02-01), Bocchino

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