Programming method of nonvolatile semiconductor memory device

Details Programming method of nonvolatile semiconductor memory device Programming method of nonvolatile semiconductor memory device

2005-10-11

2005-10-11

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

06954380

ABSTRACT:
This invention provides a programming method of a nonvolatile semiconductor device capable of programming multi-value data of three or more values rapidly. If between two threshold voltage ranges corresponding to respective memory states before and after programming, at least one threshold voltage range corresponding to other memory states exists in a programming target memory cell, a first programming step of applying at least one first program gate voltage corresponding to at least one of other memory states and a predetermined program drain voltage to a programming target memory cell is executed, then a second programming step of applying a second program gate voltage corresponding to a programmed state after programming and a predetermined program drain voltage is executed, and thereafter a verification step of verifying whether or not a program is made in a programming target memory cell is executed.

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Campardo, G. et al. (Nov. 2000). “40-mm23-V-Only 50-MHz 64-Mb 2-b/cell CHE NOR Flash Memory,”IEEE Journal of Solid-State Circuits35(11):1655-1667.
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Takeuchi, K. et al. (Apr. 1996). “A Double-Level-VthSelect Gate Array Architecture for Multilevel NAND Flash Memories,”IEEE Journal of Solid-State Circuits31(4):602-609.

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