Static information storage and retrieval – Read/write circuit – Erase
Patent
1993-11-15
1995-06-13
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Erase
365185, 365201, 365900, G11C 700
Patent
active
054249937
ABSTRACT:
A programming method for flash erasable programmable memory devices (flash EPROMs) comprises a first step of erasing the array of cells, then applying a control gate voltage to access a number of control gates. Any number of control gates can be accessed, but accessing four or eight control gates may have advantages. Regardless of the number of control gates accessed, a digit line voltage is applied to access one of the digit lines, which activates a number of cells. The digit line voltage is sensed for a voltage drop, which indicates the presence of at least one over-erased activated cell. If a digit line voltage drop is detected, a sense voltage is applied to each of the activated cells to determine which is over-erased. A heal voltage is applied to the over-erased cell for an interval of time to store electrons on the floating gate of the over-erased cell. The sense voltage is applied to the over-erased cell to determine if the cell remains over-erased, and if the cell remains over-erased the heal voltage is again applied to the over-erased cell. The sense voltage is then applied to the over-erased cell to determine if it remains over-erased.
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Yamada et al., "A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash EEPROM", IEDM Sep. 1991, pp. 307-310.
Kazerounlan et al., "A 5 Volt High Density Poly-Poly Erase Flash EPROM Cell", IEDM Aug. 1988, pp. 436-439.
Gonzalez Fernando
Lee Roger R.
Martin Kevin D.
Micro)n Technology, Inc.
Nguyen Tan
Popek Joseph A.
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