Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate
2011-07-26
2011-07-26
Yoha, Connie C (Department: 2827)
Static information storage and retrieval
Read/write circuit
For complementary information
C365S185110, C365S185170, C365S185180
Reexamination Certificate
active
07986573
ABSTRACT:
During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines. Dedicated power supplies can be used to provide the step up to avoid a risk that the unselected bit lines begin floating due to pre-charging of other bit lines The selected bit lines are coupled higher as a function of their proximity to unselected bit lines, and in preparation for applying a program pulse. Coupling may be used for slow and fast programming modes. A dedicated power supply can be provided for driving slow programming mode bit lines at a level which provides coupling compensation.
REFERENCES:
patent: 6661707 (2003-12-01), Choi et al.
patent: 6930921 (2005-08-01), Matsunaga et al.
patent: 6956770 (2005-10-01), Khalid
patent: 7064980 (2006-06-01), Cernea
patent: 7206235 (2007-04-01), Lutze
patent: 7215574 (2007-05-01), Khalid
patent: 7242616 (2007-07-01), Takeuchi
patent: 7313023 (2007-12-01), Li
patent: 7400534 (2008-07-01), Maejima
patent: 7447079 (2008-11-01), Nguyen
patent: 7506113 (2009-03-01), Li
patent: 7508721 (2009-03-01), Li
patent: 2003/0048662 (2003-03-01), Park et al.
patent: 2005/0057965 (2005-03-01), Cernea et al.
patent: 2006/0034140 (2006-02-01), Ogawa
patent: 2006/0120165 (2006-06-01), Hemink
patent: 2009/0059660 (2009-03-01), Lee
patent: 1324343 (2003-07-01), None
International Search Report and The Written Opinion of the International Searching Authority dated Mar. 4, 2011, International Application No. PCT/US2010/057667 filed Nov. 22, 2010.
U.S. Appl. No. 12/547,449, filed Aug. 25, 2009.
U.S. Appl. No. 12/624,584, filed Aug. 24, 2009.
U.S. Appl. No. 12/624,595, filed Aug. 24, 2009.
SanDisk Technologies Inc.
Vierra Magen Marcus & DeNiro LLP
Yoha Connie C
LandOfFree
Programming memory with direct bit line driving to reduce... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programming memory with direct bit line driving to reduce..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming memory with direct bit line driving to reduce... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2666885