Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-01-26
2010-12-28
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07861139
ABSTRACT:
Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combining a block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combining the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector.
REFERENCES:
patent: 6119259 (2000-09-01), Jeong
patent: 6539512 (2003-03-01), Jeong et al.
patent: 2004/0083334 (2004-04-01), Chang et al.
patent: 2005/0055610 (2005-03-01), Sassa et al.
patent: 2007/0113154 (2007-05-01), Kojima
Murray Michael
Radke William Henry
Lamarre Guy J
Micro)n Technology, Inc.
Schwegman Lundberg & Woessner, P.A.
LandOfFree
Programming management data for NAND memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programming management data for NAND memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming management data for NAND memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4165912