Programming error correction code into a solid state memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Details

C714S718000, C714S764000, C714S774000, C714S799000, C365S185090, C365S201000

Reexamination Certificate

active

08006166

ABSTRACT:
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

REFERENCES:
patent: 7275190 (2007-09-01), Roohparvar
patent: 7650541 (2010-01-01), Roohparvar
patent: 7916536 (2011-03-01), Roohparvar et al.
patent: 2003/0217323 (2003-11-01), Guterman et al.
patent: 2005/0086574 (2005-04-01), Fackenthal
patent: 2006/0098484 (2006-05-01), Roohparvar
patent: 2007/0168840 (2007-07-01), Roohparvar
patent: 2008/0310225 (2008-12-01), Roohparvar
patent: 0 802 540 (1997-10-01), None
patent: WO 2006/013529 (2006-02-01), None

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