Programming differently sized margins and sensing with...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S189140, C365S189150, C365S189160, C365S185170, C365S185220

Reexamination Certificate

active

07606084

ABSTRACT:
Non-volatile memory read operations compensate for floating gate coupling when the apparent threshold voltage of a memory cell may have shifted. A memory cell of interest can be read using a reference value based on a level of charge read from a neighboring memory cell. Misreading the neighboring cell may have greater effects in particular programming methodologies, and more specifically, when reading the neighboring cell for particular states or charge levels in those methodologies. In one embodiment, memory cells are programmed to create a wider margin between particular states where misreading a neighboring cell is more detrimental. Further, memory cells are read in one embodiment by compensating for floating gate coupling based on the state of a neighboring cell when reading at certain reference levels but not when reading at other reference levels, such as those where a wider margin has been created.

REFERENCES:
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5764572 (1998-06-01), Hammick
patent: 5867429 (1999-02-01), Chen et al.
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6055181 (2000-04-01), Tanaka et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6259632 (2001-07-01), Khouri et al.
patent: 6377507 (2002-04-01), Tsao
patent: 6496412 (2002-12-01), Shibata et al.
patent: 6522580 (2003-02-01), Chen et al.
patent: 6535423 (2003-03-01), Trivedi et al.
patent: 6542407 (2003-04-01), Chen et al.
patent: 6570790 (2003-05-01), Harari
patent: 6594181 (2003-07-01), Yamada
patent: 6643188 (2003-11-01), Tanaka et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 6717847 (2004-04-01), Chen
patent: 6771536 (2004-08-01), Li et al.
patent: 6781877 (2004-08-01), Cernea et al.
patent: 6785169 (2004-08-01), Nemati et al.
patent: 6798698 (2004-09-01), Tanaka et al.
patent: 6807095 (2004-10-01), Chen et al.
patent: 6847555 (2005-01-01), Toda
patent: 6870766 (2005-03-01), Cho et al.
patent: 6870768 (2005-03-01), Cernea et al.
patent: 6888758 (2005-05-01), Hemink et al.
patent: 6956770 (2005-10-01), Khalid et al.
patent: 7012835 (2006-03-01), Gonzalez et al.
patent: 7020017 (2006-03-01), Chen et al.
patent: 7031214 (2006-04-01), Tran
patent: 7057935 (2006-06-01), Chevallier
patent: 7057936 (2006-06-01), Yaegashi et al.
patent: 7099194 (2006-08-01), Tu et al.
patent: 7173859 (2007-02-01), Hemink
patent: 7187585 (2007-03-01), Li et al.
patent: 7187592 (2007-03-01), Guterman et al.
patent: 7196928 (2007-03-01), Chen
patent: 7196946 (2007-03-01), Chen et al.
patent: 7221598 (2007-05-01), Jeong
patent: 7230855 (2007-06-01), Chevallier
patent: 7352628 (2008-04-01), Kamei
patent: 2003/0137888 (2003-07-01), Chen
patent: 2003/0161182 (2003-08-01), Li et al.
patent: 2004/0047182 (2004-03-01), Cernea et al.
patent: 2004/0057283 (2004-03-01), Cernea
patent: 2004/0057285 (2004-03-01), Cernea et al.
patent: 2004/0057287 (2004-03-01), Cernea et al.
patent: 2004/0057318 (2004-03-01), Cernea et al.
patent: 2004/0060031 (2004-03-01), Cernea
patent: 2004/0109357 (2004-06-01), Cernea et al.
patent: 2004/0136220 (2004-07-01), Cohen
patent: 2004/0213031 (2004-10-01), Koji
patent: 2005/0117401 (2005-06-01), Chen et al.
patent: 2005/0162913 (2005-07-01), Chen
patent: 2006/0285391 (2006-12-01), Cernea
patent: 2008/0144368 (2008-06-01), Kamei
patent: 2008/0158996 (2008-07-01), Kamei
patent: 01271553 (2003-01-01), None
patent: 01329898 (2003-01-01), None
Kamei, Teruhiko, “Systems for Programming Differently Sized Margins and Sensing with Compensations at Select States for Improved Read Operations in Non-Volatile Memory,” U.S. Appl. No. 11/425,116, filed Jun. 19, 2006.
Restriction, United States Patent & Trademark Office, U.S. Appl. No. 11/425,116, filed on Jun. 19, 2006, Aug. 29, 2007.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 11/425,116, filed on Jun. 19, 2006, Nov. 7, 2007.
Response to Restriction Requirement, U.S. Appl. No. 11/425,116, filed on Jun. 19, 2006, Oct. 1, 2007.
International Search Report & The Written Opinion of the International Searching Authority, Patent Cooperation Treaty, Application No. PCT/US2007/069713 filed May 25, 2007, Mar. 4, 2008.
Jung, et al., “A 117-mm23.3-V Only 128-Mb Multilevel NAND Flash Memory For Mass Storage Applications,” IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US, vol. 31, No. 11, Nov. 1996, pp. 1575-1583.
Notice of Allowance and Fee(s) Due, United States Patent & Trademark Office, U.S. Appl. No. 12/038,407, filed on Feb. 27, 2008, Oct. 21, 2008.
Non-Final Office Action, United States Patent & Trademark Office, U.S. Appl. No. 12/038,421, filed Feb. 27, 2008, Dec. 23, 2008.
Response to Non-Final Office Action dated Mar. 23, 2009, U.S. Appl. No. 12/038,421, filed Feb. 27, 2008.
Notice of Allowance & Fee(s) Due dated Jun. 18, 2009, United States Patent & Trademark Office, U.S. Appl. No. 12/038,421 filed Feb. 27, 2008,.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Programming differently sized margins and sensing with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programming differently sized margins and sensing with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programming differently sized margins and sensing with... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4090165

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.