Programming circuits and techniques for programmable logic

Details Programming circuits and techniques for programmable logic Programming circuits and techniques for programmable logic

2000-04-06

2003-10-21

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S100000, C711S165000, C711S170000

Reexamination Certificate

active

06636936

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programming techniques for configuring multiple programmable integrated logic circuits. In particular, the invention relates to improved techniques and methods to configure a plurality of programmable logic devices from nonvolatile memory.
Programmable logic devices (PLDs), sometimes referred to as PALs, PLAs, FPLAs, PLDs, FPLDs, EEPLDs, LCAs, and FPGAs, and the like are well known. PLDs allow users to electrically program off-the-shelf logic elements to meet the specific needs of their applications. Multiple PLDs can be interconnected to implement complex logic functions. As such, PLDs permit users to combine the logistical advantages of standard, fixed integrated circuits with the architectural flexibility of custom devices. Proprietary logic functions can be designed and fabricated in-house, eliminating the long engineering lead times, high tooling costs, complex procurement logistics, and dedicated inventory problems associated with custom devices.
PLDs often comprise a plurality of logic blocks and interconnections which are configurable to perform user-specified logic operations. These PLDs are often implemented using reprogrammable memory cells. One type of PLD uses reprogrammable CMOS SRAM cells to configure the logic blocks and interconnections. To enable the PLD to perform a desired logic function, the PLD must first be configured. The process of loading the programming data into one or more PLDs is called configuration. Programming or configuration data for the PLD device is often stored in a configuration EPROM device or provided to the PLD by an intelligent host such as a CPU, system controller, and the like from nonvolatile memory.
Altera Corporation of San Jose, Calif., produces a variety of PLDs such as the FLEX 8000™, described in detail in the August 1993 Datasheet, or the MAX 7000™ described in detail in the September 1991 ALTERA DATABOOK, both incorporated herein for all purposes. Altera also produces software and hardware tools to simplify the design of complex logic circuits using PLDs. Further references can be made to the documentation which accompanies the MAX+PLUSII™ development system, Altera Logic Programmer Card, and the Master Programming Unit. The use of the aforementioned hardware and software tools for designing PLDs is common knowledge to those of skill in the art.
Traditional designs permit the configuration of a single PLD on power-up. However, as logic functions grow more complex, multiple PLDs are frequently used to implement the logic circuitry. From a circuit designer's perspective, it is highly desirable to implement configuration using a circuit which can efficiently configure multiple PLDs while keeping overhead configuration circuitry to a minimum to save space and costs.
The use of reprogrammable memory cells to implement PLDs also permits on-demand reconfiguration. Unlike power-on configuration schemes, on-demand reconfiguration permits the user or the software to dynamically reconfigure an entire system using configuration data stored on nonvolatile media. The PLDs can be reconfigured when triggered by a predefined condition, such as the detection of a momentary power failure. On-demand configuration enables the user to perform in-circuit upgrades and modifications without having to remove the PLDs from the application circuity. Reconfigurability also permits the user to reuse the logic resources of the PLD instead of designing redundant or duplicate circuitry into the system. For some applications, timing considerations require that the configuration circuitry accomplishes on-demand reconfiguration of the PLDs with a minimum time delay.
There is thus a need for improved configuration circuits and techniques, which are simple, inexpensive, and efficient, for configuring multiple PLDs. The circuitry preferrably accomplishes reconfiguration in a minimum amount of time and adaptable to either on-demand or power-up configuration.
SUMMARY OF THE INVENTION
The present invention relates to apparatus and methods for configuring a plurality of programmable logic devices. The configuration method includes the steps of providing a source of configuration data and transferring via a direct data path the configuration data from the source to each programmable logic device. In one embodiment, the source of configuration data is preferably one or more nonvolatile memory chip such as an EPROM, EEPROM, and the like. In another embodiment, the configuration data is stored in one or more configuration data files on magnetic and/or optical memory. Depending on which configuration circuit or method is selected, the configuration of the programmable logic devices is accomplished in a parallel, sequential, or interleaved manner.


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