Programming architecture for field programmable gate array

Details Programming architecture for field programmable gate array Programming architecture for field programmable gate array

1998-09-01

2001-01-02

Santamauro, Jon (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C327S525000

Utility Patent

active

06169416

ABSTRACT:

BACKGROUND INFORMATION
FIG. 1
(Prior Art) is a simplified top-down diagram of a programming structure of a field programmable gate array (FPGA) integrated circuit
1
employing antifuses. For additional background information on such an FPGA, its programming structure, and testing structures, see U.S. patent application Ser. No. 08/667,702, entitled “Programming Architecture For A Programmable Integrated Circuit Employing Antifuses”, filed Jun. 21, 1996, by Kolze et al. now U.S. Pat. No. 5,825,201; and U.S. Pat. No. 5,495,181 entitled “Integrated Circuit Facilitating Simultaneous Programming Of Multiple Antifuses” by Kolze (the subject matter of this application and this patent is incorporated herein by reference in its entirety).
FPGA
1
includes four logic regions
2
-
5
of logic cells and programmable interconnect employing antifuses. Four of the antifuses can be programmed at once, one in each logic region. The programming current for each antifuse is supplied from a different programming current terminal so it can be assured that each of the four antifuses has been programmed with an adequate amount of programming current. For example, antifuse
6
could by programmed with a programming current from programming current terminal VppA, antifuse
7
could be programmed with a programming current from programming current terminal VppB, antifuse
8
could be programmed with a programming current from programming current terminal VppC, and antifuse
9
could be programmed with a programming current from programming current terminal VppD.
Programming current is supplied to antifuse
6
by controlling programming current multiplexer
10
to couple L-shaped VppA programming power bus
1
I
1
to programming bus
12
. Programming driver
13
drives the voltage (VppA) on programming bus
12
onto vertically extending programming conductor
14
. Likewise, programming current multiplexer
15
is controlled to couple rectangular ground bus
16
to programming bus
17
. As a result, programming driver
18
drives the voltage (GND) on programming bus
17
onto vertically extending programming conductor
19
. A programming control driver
20
drives a programming control conductor
21
such that programming transistors
22
and
23
are conductive. Programming current flows from programming current terminal VppA, through L-shaped VppA programming power bus
11
, through programming current multiplexer
10
, through programming bus
12
, through programming driver
13
, through programming conductor
14
, through conductive programming transistor
22
, through routing conductor
24
, through antifuse
6
, through routing conductor
25
, through conductive programming transistor
23
, through programming conductor
19
, through programming driver
18
, through programming bus
17
, through programming current multiplexer
15
, through rectangular ground bus
16
, and to programming current terminal GND.
Antifuses
7
,
8
, and
9
are programmed in similar fashion with programming current multiplexers
26
-
31
being controlled so that the voltages indicated on
FIG. 1
are supplied onto the programming conductors as indicated. Each of the four antifuses is programmed with a different programming current supplied from a different programming current terminal. Because a different programming current flows through each of the four antifuses, it can be assured that each of the four antifuses was in fact programmed with an adequately large programming current.
If antifuse
32
were, however, the antifuse chosen for simultaneous programming in logic region
3
, then it could not be assured that each of the four antifuses was programmed with an adequately large programming current. Programming driver
33
would supply programming current at voltage VppD onto programming conductor
34
, but it would not be known how much of this programming current flowed through antifuse
9
and how much flowed through antifuse
32
. One of these antifuses may conduct all or most of the programming current such that the other antifuse is not programmed or is inadequately programmed. It is therefore seen that an antifuse in one logic region cannot necessarily be programmed simultaneously with any antifuse in another logic region. A programming architecture is sought wherein an antifuse in one logic region can be programmed at the same time that an antifuse is programmed in each of the other three logic regions irrespective of which particular other antifuses are being programmed in those other logic regions.
SUMMARY
The programmable logic of a programmable device is sectioned into four logic regions. Each logic region includes logic elements and a programmable interconnect structure employing antifuses for programmably interconnecting selected logic elements. Programming conductors for supplying programming current to antifuses of a logic region extend across the logic region but do not extend across other logic regions. Similarly, programming control conductors that control programming transistors of the logic region extend across the logic region but do not extend across other logic regions. The programmable device structure allows four antifuses to be programmed simultaneously, one antifuse in each logic region. An antifuse can be selected for simultaneous programming from a logic region, irrespective of the other three antifuises that are or may be selected for simultaneous programming from the other three logic regions. Four programming current multiplexers and four programming buses are provided for each logic region so that the programming current that programs each antifuse flows from a separate input terminal. The resistance of the programming conductors is reduced by the use of parallel strips of metal in multiple metal layers.
This summary does not purport to define the invention. The invention is defined by the claims.


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