Programming architecture for a programmable integrated circuit e

Details Programming architecture for a programmable integrated circuit e Programming architecture for a programmable integrated circuit e

1996-06-21

1998-10-20

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, H03K 19177

Patent

active

058252010

ABSTRACT:
A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. In one aspect, the number of programming conductors and the number of perpendicular programming control conductors for a logic module are substantially equal. In another aspect, programming current is supplied onto long routing wire segments via two programming transistors and two programming conductors. In another aspect, a pattern of programming drivers alternates from one side of the integrated circuit to the opposite side from one column of macrocells to the next. In other aspects, control conductors and programming conductors are tested with test antifuses and test transistors. In another aspect, adjacent logic modules have mirrored structures so that they can share an intervening programming conductor resource. In another aspect, L-shaped programming power busses are provided and in another aspect, an express wire is simultaneously driven with programming current from two different programming voltage terminals. In other aspects, a test circuit tests the integrity of collinear routing wire segments and output programming transistors are tested. In another aspect, antifuses on branches of clock conductors are programmed.

REFERENCES:
patent: 5194759 (1993-03-01), El-Ayat et al.
patent: 5196724 (1993-03-01), Gordon et al.
patent: 5220213 (1993-06-01), Chan et al.
patent: 5302546 (1994-04-01), Gordon et al.
patent: 5327024 (1994-07-01), Cox
patent: 5336986 (1994-08-01), Allman
patent: 5347519 (1994-09-01), Cooke et al.
patent: 5391942 (1995-02-01), El-Ayat et al.
patent: 5416367 (1995-05-01), Chan et al.
patent: 5424655 (1995-06-01), Chua
patent: 5495181 (1996-02-01), Kolze
patent: 5498979 (1996-03-01), Parlour et al.
patent: 5502315 (1996-03-01), Chua et al.
patent: 5544070 (1996-08-01), Cox et al.
patent: 5557136 (1996-09-01), Gordon et al.
Xilinx, "The Programmable Gate Array Design Book", First Edition, pp. 1-9 thru 2-73 (1986).
U.S. application No. 07/892,466, filed Jun. 1992, pending.
U.S. application No. 08/541,662, filed Oct. 1995, pending.
S. Trimberger, "Field Programmable Gate Array Technology", pp. 1-14 and 98-170, (1994).
S. Brown et al., "Field Programmable Gate Arrays", pp. 1-43 and 88-202, (1992).
D. Pellerin and M. Holley, "Practical Design Using Programmable Logic" pp. 84-98, (1991).
Advanced Micro Device, PAL Device Data Book and Design Guide, pp. 2-236 through 2-247, (1993).
Quicklogic Data Book, pp. 1-5 through 2-11 and 6-3 through 6-18, (1995).
Actel FPGA Data Book and Design Guide, pp. ix-xv, 1-5 through 1-34, 1-51 through 1-101, 1-153 through 1-222, 3-1 through 4-56, (1995).
C. Erickson, et al., "Logic Cell Array", The Programmable Gate Array Design Book, First Edition, pp. 1-9 thru 2-73, (1986).

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