Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent
1995-11-08
1998-09-01
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
711219, 326 39, G06F 1202
Patent
active
058025405
ABSTRACT:
A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.
REFERENCES:
patent: 4791603 (1988-12-01), Henry
patent: 5128559 (1992-07-01), Steele
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5469400 (1995-11-01), Yamano
patent: 5550782 (1996-08-01), Cliff et al.
John L. Nichols, "A Logical Next Step for Read-Only Memories", Electronics, Jun. 12, 1967, pp. 111-113.
Floyd Kvamme, "Standard Read-Only Memories Simplify Complex Logic Design", Electronics, Jan. 5, 1970, pp. 88-95. Easily", Electronics, May, 11, 1970, pp. 104-111.
William I. Fletcher et al., "Simplify Sequential Circuit Designs", Electronic Design, Jul. 8, 1971, pp. 70-72.
Howard A. Sholl et al., l"Design of Asynchronous Sequential Networkds Using Read-Only Memories", IEEE Transactions on Computers, vol. C-24, No. 2, Feb. 1975, pp. 195-206.
Aronld Weinberger, "High-Speed Programmable Logic Arrays Adders", IBM J. Res. Develop., vol. 23, No. 2, Mar. 1979, pp. 163-178.
Yahiko Kambayashi, "Logic Design of Programmable Logic Arrays", IEEE Transactions on Computers, vol. c-28, No. 9, Sep. 1979, pp. 609-617.
Chang Wanli
Huang Joseph
Sung Chiakang
Altera Corporation
Chan Eddie P.
Jackson Robert R.
Portka Gary J.
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