Static information storage and retrieval – Systems using particular element – Amorphous
Reexamination Certificate
2003-04-01
2004-02-03
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Systems using particular element
Amorphous
C365S113000, C365S148000
Reexamination Certificate
active
06687153
ABSTRACT:
BACKGROUND
This invention is related to techniques for programming a structural phase-change material solid state memory device such as those that use a chalcogenide material which can be programmed into different resistivity states to store data.
Solid state memory devices that use a structural phase-change material as the data storage mechanism (referred to here simply as ‘phase-change memories’) offer significant advantages in both cost and performance over conventional charge storage based memories. The phase-change memory is made of an array of constituent cells where each cell has some structural phase-change material to store the cell's data. This material may be, for instance, a chalcogenide alloy that exhibits a reversible structural phase change from amorphous to crystalline. A small volume of the chalcogenide alloy is integrated into a circuit that allows the cell to act as a fast switching programmable resistor. This programmable resistor can exhibit greater than 40 times dynamic range of resistivity between the crystalline state (low resistivity) and the amorphous state (high resistivity), and is also capable of exhibiting multiple, intermediate states that allow multi-bit storage in each cell. The data stored in the cell is read by measuring the cell's resistance. The chalcogenide alloy cell is also non-volatile.
A conventional technique for programming a phase-change memory cell is to apply a rectangular pulse of current (having a constant magnitude) to the cell, at a voltage greater than a switching threshold for the phase-change material, which leaves the material in the reset state (amorphous and high resistivity). This may be followed by the application of a subsequent rectangular pulse, also at a voltage greater than the switching threshold, which changes the material to a set state (crystalline and low resistivity). The reset pulse has a higher magnitude of current than the set pulse so that the temperature of the phase change material is raised to T
m
, the amorphizing temperature, before the material is rapidly cooled down and is left in the amorphous state to change into the crystalline state, the material can be heated back up to an optimum temperature T
opt
, which is lower than T
m
. The temperature T
opt
is that which allows the material in the cell to be crystallized in a relatively short time interval and yielding a relatively low resistance. Ideally, this could be accomplished by having the magnitude of the set pulse be smaller than that of the reset pulse to prevent the phase-change material from reaching the amorphizing temperature, but large enough to cause the material to reach T
opt
.
Because of fabrication process and material variations in phase change memories, the actual temperature of the phase-change material in the cells of a manufactured device varies significantly from cell to cell, for a given programming current/voltage level obtained by a set pulse. This variation can cause the material in one or more cells of a device to inadvertently reach T
m
during application of the conventional rectangular set pulse, and thereby cause those cells to erroneously remain in the reset state rather than change to the set state. To avoid this problem, conventional programming techniques use a rectangular set pulse (applied to every cell in the device) that has a reduced magnitude, as shown in FIG.
1
. The magnitude of the set current is sufficiently low, in view of the expected variation in cell temperature at that magnitude, to guarantee that no cell in the device reaches Tm while the set pulse is applied to it. This solution, however, may slow down the programming of the memory device, since a longer rectangular set pulse is needed due to the less than optimal temperatures being generated by the lower magnitude of the set pulse. In addition, many cells in the memory are subjected to significantly less than the optimum crystallization temperature which reduces the dynamic range in resistivity between the set and reset states in those cells.
REFERENCES:
patent: 6339544 (2002-01-01), Chiang et al.
patent: 6487113 (2002-11-01), Park et al.
patent: 6625054 (2003-09-01), Lowrey et al.
patent: 1 372 414 (1974-10-01), None
Le Toan
Nguyen Van Thu
Ovonyx Inc.
Trop Pruner & Hu P.C.
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