Programming a memory device having error correction logic

Details Programming a memory device having error correction logic Programming a memory device having error correction logic

2006-08-30

2009-11-24

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07624329

ABSTRACT:
Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an error correction enabled mode to an error correction disabled mode and programming at least the main portion of at least one addressable unit of the non-volatile memory array in the error correction disabled mode. The exemplary method further includes, in response to a second condition, switching from the error correction disabled mode to an error correction fill mode and programming at least the error correction portion of the at least one addressable unit of the non-volatile memory array in the error correction fill mode.

REFERENCES:
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patent: 6760805 (2004-07-01), Lasser
patent: 7424648 (2008-09-01), Honda
patent: 7469368 (2008-12-01), Chen et al.
patent: 2004/0264271 (2004-12-01), Tanzawa et al.
patent: 2005/0243626 (2005-11-01), Ronen

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