Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-08-28
2004-04-27
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06728148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including a programmable element, and a technique for achieving both a reduction of leak current and a decrease of the area of the programmable element. In particular, the present invention relates to a technique for achieving both a decrease of the area of a fuse element or the like and a reduction of leak current flowing through a residual resistance thereof in a memory block on which a plurality of programmable elements have to be mounted for redundancy repair.
2. Description of the Related Art
Conventionally, in general, a fuse element is utilized as a programmable element, for example, used in a memory block, and the presence or the absence of a program generally is set by either irradiating the fuse element with laser to melt and cut (blow) the fuse element or not doing so. However, in order to blow the fuse element with high precision, it is necessary to adjust the power of the laser for irradiation.
FIGS. 12A
,
12
B and
12
C are circuit diagrams showing an example of the configuration of a conventional programmed value determining circuit employing a fuse element as a programmable element used in a memory block and the like.
FIG. 12A
shows a state in which there is no program before a fuse element
100
is blown.
FIG. 12B
shows a state in which there is a program after the fuse element
100
has been blown with a high laser power.
FIG. 12C
shows a state in which there is a program after the fuse element
100
has been blown with a low laser power.
In
FIG. 12A
, when a voltage with a logic “H” level is applied to an input node N
1
, a PMOS transistor Qp
1
in the first stage is turned off, and an NMOS transistor Qn
1
in the first stage is turned on. Since the fuse element
100
is connected, an intermediate node (storage node) N
2
is in a logic “L” level, which is the electric potential of the ground line VSS, and a PMOS transistor Qp
3
in the second stage is turned on and an NMOS transistor Qn
2
in the second stage is turned off, so that a voltage with a logic “H” level, which is the electric potential of the power line VDD, is output to an output node N
3
. Thus, a PMOS transistor Qp
2
is turned off. This is the state in which there is no program.
On the other hand, in
FIGS. 12B and 12C
in which the fuse element
100
is blown, when a voltage with a logic “H” level is applied to an input node N
1
, a PMOS transistor Qp
1
in the first stage is turned off, and an NMOS transistor Qn
1
is turned on. However, since the fuse element
100
is cut off, the intermediate node N
2
becomes in a logic “H” level, which is the electric potential of the power line VDD, by turning the PMOS transistor Qp
2
on, and the PMOS transistor Qp
3
in the second stage is turned off and an NMOS transistor Qn
2
in the second stage is turned on, so that a voltage with a logic “L” level, which is the electric potential of the ground line VSS is output to an output node N
3
. This is the state in which there is a program.
As shown in
FIG. 12B
, in order to blow the fuse element
100
completely (the residual resistance of the fuse element
100
is, for example, 1 M ohm or more), it is sufficient to increase the power of the laser for irradiation, but the fuse elements in the vicinity thereof may be melted and cut. Therefore, when providing a plurality of fuse elements, the area may increase because the distance between the adjacent fuse elements is increased or transistors cannot be laid out in the adjacent regions.
On the other hand, when the power of the laser for irradiation is low, an irradiation point also is small, so that the influence on the adjacent region can be small. However, the residual resistance of the fuse element
100
becomes low (e.g., 10 k ohm or less), so that a leak current Ileakflows from the power line VDD to the ground line VSS through the PMOS transistor Qp
2
and the NMOS transistor Qn
1
, as shown in FIG.
12
C.
FIG. 13
is a graph showing the relationship of the residual resistance Rfuse and the leak current Ileak caused to flow thereby after the fuse element
100
has been blown, with respect to the fuse pitch Hpitch and the relative laser power Lpower.
As shown in
FIG. 13
, when the fuse pitch Hpitch is small and the relative laser power Lpower is small, the fuse element
100
is melted and cut completely in some cases, and in other cases, it is not completely melted and cut, which creates instability, so that the residual resistance Rfuse are varied significantly. In particular, when the residual resistance Rfuse becomes small, the leak current Ileak becomes large. Therefore, conventionally, there is a trade-off between the fuse pitch Hpitch, that is, the area and the leak current Ileak.
In the future, process miniaturization will be promoted, and a large number of functions will be integrated. With this trend, it becomes more important to constitute a circuit that implements a defect recovery function with FPGA (Field Programmable Gate Array) or the like, so that it is expected that a demand for program elements that are mounted on an LSI will be increased rapidly. In this case, the area of the programmable elements will be an issue.
In addition to blowing the fuse element as described above, in order to form a programmable element, a polysilicon line can be melted and cut by applying a high voltage, or a high voltage stress is applied to increase the threshold voltage, as is the case with a flash memory. However, in all of these methods, the programmable element has to be spaced apart from adjacent devices or the area thereof has to be increased in order to change the resistance or the threshold voltage stably.
When reducing the area to increase the degree of integration, the change in the resistance of the polysilicon line or the change in the threshold voltage of the flash memory may become insufficient, and the problem of leak current is likely to be induced.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a programmed value determining circuit in which there is no relationship of a trade-off between the area of the programmable element and the leak current, and both the area of the programmable element and the leak current are reduced, and provide a semiconductor integrated circuit device having the programmed value determining circuit and a method for determining a programmed value.
A programmed value determining circuit of the present invention includes a programmable element whose resistance is changed depending on whether or not there is a program, a detecting portion including a first circuit and a second circuit, and latch means. The first circuit includes first and second switching elements that operate in response to first and second control signals respectively, and are connected to the program element in series between a first power terminal and a second power terminal. At least the first switching element is inserted between the first power terminal and an intermediate connection node. At least the second switching element connected to the programmable element in series is inserted between the intermediate connection node and the second power terminal. The second circuit converts an electric potential at the intermediate connection node to a logic level and outputting it to an output node. The latch means latches the electric potential at the intermediate connection node to make the intermediate connection node act as a storage node of a programmed value of the programmable element. During a second period subsequent to the first period after power is turned on, at least the second switching element is turned on, the storage node is connected to the second power terminal via the programmable element, and the state of the storage node is detected by the detecting portion. During a third period after the second period, both the first and the second switching elements are turned off, and the state of the storage node is held by the latch
Merchant & Gould P.C.
Phan Trong
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