Programmed memory with improved speed and power consumption

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement

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Details

365 94, 36523003, G11C 1604

Patent

active

059403322

ABSTRACT:
A memory for storing a reorganizing array of an initial array of data of binary ones and zeros to enable decoding of the reorganized array to reproduce the information content of the initial array, and the method of reorganizing the initial array. The memory includes a data circuit array that has a plurality of memory cells arranged in rows and columns for storing the reorganized array. The memory also has a plurality of flag memory cells and a row of XOR gates and inverters. The initial array is divided into sections. Each row of each section of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. Each column of the initial array that has more ones than zeros is inverted, and the corresponding flag bit is also inverted. This is repeated until each row in each section and each column has at least as many ones as zeros, producing the reorganized array. The reorganized array is stored in the data circuit array, and the flag bits corresponding to each row of each section are stored in the flag memory cells. Each XOR gate is connected to one column of the memory cells and to the column of the flag memory cells that correspond to the column of memory cells. An inverter is connected only to the columns whose corresponding flag bit is a one. In an alternative embodiment, the memory contains XOR gates and flag memory columns but not the inverters. In another alternative embodiment, the memory contains inverters but not the XOR gates or flag memory cells. A memory for storing the reorganizing array reduces the number of ones stored in the memory, reducing the memory's power consumption and increasing its access time.

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