Programmed access latency in mock multiport memory

Details Programmed access latency in mock multiport memory Programmed access latency in mock multiport memory

2007-06-12

2007-06-12

Lee, Christopher E. (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

Decentralized arbitrating

C710S316000, C711S149000, C711S167000

Reexamination Certificate

active

10515463

ABSTRACT:
A computer memory arrangement comprises a first plurality of input port facilities (17–19) that are collectively coupled through a first router facility (32) to selectively feed a second plurality of memory modules (20–24). It furthermore comprises an output port facility that is collectively fed by said second plurality of memory modules (20–24). In particular, the computer memory arrangement comprises a detection facility (36–40) conflicting accesses through more than one of the first plurality of input port facilities, and for thereupon allowing only a single one among said simultaneous and conflicting accesses whilst generating a stall signal for signalling a mandatory stall cycle to a request source that implies an access latency thereto. The computer memory furthermore comprises a programming facility for having the access latency be selectably programmable according to an actual processing application.

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