Programmable VESA unified memory architecture (VUMA) row address

Details Programmable VESA unified memory architecture (VUMA) row address Programmable VESA unified memory architecture (VUMA) row address

1996-05-22

1999-04-20

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711202, 711148, 711105, 395299, 365193, 36523002, 36523006, G06F 1202, G11C 700, G11C 800

Patent

active

058954813

ABSTRACT:
A memory controller is disclosed for use in physically mapping a VESA Unified Memory Architecture (VUMA) device, Row Address Strobe signal RAS# to a selected one of a plurality of memory banks. The RAS# signal from the VUMA device is routed to the memory controller, not the memory bank directly. The memory controller employs a network of pass gates to provide an electrically-conductive channel for routing the VUMA device RAS# signal to the appropriate memory bank. The appropriate pass gate is caused to become conductive through the use of a decoder, and a 3-bit clocked register bank. The register bank is programmable to generate a select signal on its output that is representative of the desired memory bank to receive the VUMA device RAS# signal. The select signal, which is a 3-bit signal, is provided to the decoder, which activates one of its plurality of output lines to thereby cause the selected pass gate to conduct. Through this conductive path, the RAS# signal can be routed to the desired memory bank for access to data stored therein.

REFERENCES:
patent: 5005157 (1991-04-01), Catlin
patent: 5414670 (1995-05-01), Schaefer
patent: 5613094 (1997-03-01), Khan et al.
VUMA Standard--Hardware Specifications, Video Electronics Association, Version 1.0, Mar. 1996.

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