Electrical transmission or interconnection systems – Plural load circuit systems – Selectively connected or controlled load circuits
Reexamination Certificate
1998-12-28
2001-05-08
Paladini, Albert W. (Department: 2836)
Electrical transmission or interconnection systems
Plural load circuit systems
Selectively connected or controlled load circuits
C340S870030
Reexamination Certificate
active
06229227
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuit (IC) chips and, more particularly, to IC chips having passive (analog) components such as resistors, capacitors, and inductors incorporated into their design (“on-chip”), such as is typical of analog and mixed signal designs.
BACKGROUND OF THE INVENTION
MOS technology (particularly CMOS technology) is currently of limited suitability for mixed signal (analog) designs. Thus, most microelectronic devices which operate with real-world signals (such as video, voice, feedback control, etc.) signals typically require both an analog circuit or multiple analog ICs along with the less costly digital IC devices.
Some (pseudo-analog) devices have been proposed for CMOS and BiCMOS devices. However pseudo-analog devices do not permit low power compressed designs therefore defeating the advantages present in a single chip MOS solution.
One of the substantial difficulties present in developing mixed signal circuits on MOS technology is the fabrication of passive components (resistors, capacitors, inductors, etc).
One of the challenging tasks faced by mixed signal designs, is providing a single chip solution. One limiting factor is to fabricate accurate passive components on-chip.
Various techniques are used to implement passive components in the monolithic Integrated circuits.
On-chip resistors typically are fabricated by base diffusion, emitter diffusion, ion-implantation or by thin-film deposition. In the MOS technology, the popular resistor implementations being diffused or polysilicon or well resistors or thin-film deposition or MOS devices themselves used as resistors. The resistor value that can be achieved by the above mentioned means can normally vary from 50 ohms to 50 Ohms, which is technology and process dependent.
On-chip capacitors typically are fabricated by poly-poly, poly-metal, metal-metal process or using MOS transistor capacitance and junction capacitance. Normally an extra layer of poly layer is added to provide efficient capacitor structure.
On-chip inductance typically is realized by synthesizing an inductive reactance with an active circuit. Passive inductance can be implemented on-chip using transmission lines. They are superior as they introduce less noise, consume less power, and have a wider bandwidth and linear operating range.
The crucial parameters to be considered for passive components are their tolerance, voltage coefficient and temperature coefficient. Each technique has its pros and cons, but none of them tend to result in accurate values. For example, a common technique
100
used for correcting the value of passive components which are resistors is by laser trimming as is shown in FIG.
1
. In this figure, a resistor
102
extends between two terminals labeled “A” and “B” on an integrated circuit (IC) chip. Conductive lines
104
and
106
extend from the terminals “A” and “B” to other circuitry (not shown) on the IC chip
102
. The resistor
102
is essentially a thin layer of resistive (partially conductive) material extending from the one terminal “A” to the other terminal “B”, and is typically in the form of a rectangle, as shown, having a length (between the terminals) and a width transverse to the length.
To trim (adjust) the resistance value of the resistor
102
, its resistance is measured, then the physical structure of the resistor
102
is altered by a process known as laser trimming, wherein a laser beam ablates the resistor material. Large resistance value corrections can be made by directing a laser beam (not shown) into the resistor material from a side thereof, partially across the width of the resistor, then along the length of the resistor, as indicated by the L-shaped notch
110
. Smaller resistance value corrections can be made by directing the laser beam (not shown) into the resistor material from a side thereof and partially across the width of the resistor as indicated by the notch
112
.
A drawback to the laser trimming technique is that it is not feasible for CMOS mass production devices. Also, it is of limited value in establishing a desired capacitance value for a capacitor or a desired inductance value for an inductor.
GLOSSARY
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the invention most nearly pertains. The following terms, abbreviations and acronyms may be used in the description contained herein:
A/D: Analog-to-Digital (converter).
ALU: Arithmetic Logic Unit.
ASIC: Application-Specific Integrated Circuit.
ATM: Asynchronous Transfer Mode
bit: binary digit.
BLP: Board-Level Product.
byte: eight contiguous bits.
C: a programming language.
CAM: Content-Addressable Memory.
CAS: Column Address Strobe.
CCD: Charge-coupled device.
CD: Compact Disc.
CISC: Complex Instruction Set Computer (or Chip).
CMOS: Complementary Metal-Oxide Semiconductor.
CODEC: Encoder/De-Coder. In hardware, a combination of A/D and D/A converters. In software, an algorithm pair.
Core: A functional block intended to be embedded and integrated in broader logic design.
CPU: Central Processing Unit.
D/A: Digital-to-Analog (converter).
DAT: Digital Audio Tape.
DBS: Direct Broadcast Satellite.
DMA: Direct Memory Access.
DRAM: Dynamic Random Access Memory.
DSP: Digital Signal Processing (or Processor).
ECC: Error Correction Code.
EDO: Extended Data Output.
EDRAM: Extended DRAM.
EEPROM: Also E2PROM. An electrically-erasable EPROM.
EPROM: Erasable Programmable Read-Only Memory.
Flash: Also known as Flash ROM. A form of EPROM based upon conventional UV EPROM technology but which is provided with a mechanism for electrically pre-charging selected sections of the capacitive storage array, thereby effectively “erasing” all capacitive storage cells to a known state.
FPGA: Field-Programmable Gate Array
G: or (Giga), 1,000,000,000.
Gbyte: Gigabyte(s).
GPIO: General Purpose Input/Output.
HDL: Hardware Description Language.
HDTV: High Definition Television
IC: Integrated Circuit.
I/F: Interface.
I/O: Input/Output.
IEEE: Institute of Electrical and Electronics Engineers
JPEG: Joint Photographic Experts Group
K: (or kilo), 1000.
kernel: a core functionality of an operating (or other software) system.
KRz: KiloHertz (1,000 cycles per second).
LAN: Local Area Network
M: (or mega), 1,000,000
MAC: Media Access Control.
Mask ROM: A form of ROM where the information pattern is “masked” onto memory at the time of manufacture.
MCM: Multi-Chip Module.
Mb Megabyte
memory: hardware that stores information (data).
MHz: MegaHertz (1,000,000 cycles per second).
MIPS: Million Instructions Per Second
MLT: Multi-Level Technology.
MPEG: Motion Picture Experts Group. Standard for encoding moving images. Also widely used for high quality audio compression.
MPU: Micro Processing Unit.
NVRAM: Non-volatile RAM.
PLL: Phase Locked Loop.
PROM: Programmable Read-Only Memory.
PWM: Pulse Width Modulation.
PLD: Programmable Logic Device.
RAS: Row Address Strobe.
RAM: Random-Access Memory.
RISC: Reduced Instruction Set Computer (or Chip).
ROM: Read-Only Memory.
RTOS: Real Time Operation System
SCM: Single Chip Module
SDRAM: Synchronous DRAM.
SIE: Serial Interface Engine.
SOC: System On a chip software: Instructions for a computer or CPU.
SRAM: Static Random Access Memory.
TCP/IP: Terminal Control Protocol/internet Protocol.
UART: Universal Asynchronous Receiver/Transmitter.
USB: Universal Serial Bus.
TV EPROM: An EPROM. Data stored therein can be erased by exposure to Ultraviolet (UV) light.
VCR: Video Cassette Recorder.
VHDL: VHSIC (Very High Speed Integrated Circuit) HDL.
WAN: Wide Area Network. Such as the telephone system or the Internet, or a satellite network.
ZISC: Zero Instruction Set Computer (or Chip).
BRIEF DESCRIPTION (SUMMARY) OF THE INVENTION
An object of the present invention is to provide an improved technique for adjusting the value of passive components on an integrated circuit (IC) chip.
Another object of the inven
Muthukumaraswamy Kumaraguru
Rostoker Michael D.
Kawasaki Steel Corporation
Linden Gerald E.
Paladini Albert W.
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