Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-04-09
2004-05-25
Thai, Xuan M. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S119000, C710S123000, C710S240000
Reexamination Certificate
active
06742064
ABSTRACT:
BACKGROUND OF THE INVENTION
In a processing system, a number of devices including a central processing unit (CPU) and memory are coupled to a time shared processor bus through which digital words are transferred from one device to another under software task control of the CPU or other control device. These control devices generally operate autonomously to perform certain tasks according to some sequence. For example, in
FIG. 1A
which is a time graph exemplifying a control device, like a CPU or DMA controller, for example, carrying out tasks
1
,
2
,
3
and
4
in a predetermined sequence. In performing these tasks, the control device generally requires access to the processor bus and more than one control device may require access to the processor bus concurrently in order to carry out their individual tasks. A bus arbiter is generally provided to regulate access to the bus among the various control devices requiring access according to a predetermined priority scheme to prevent collisions. However, when permitted, access is limited to the performance of only one or two cycles of the task, but not the entire task in order to prevent any one control device from dominating access to the bus.
Certain tasks carried out by the control devices are considered critical from the perspective that they must be performed within an absolute maximum time (AMT). Each critical task may have its own individual AMT based on the real time application being performed. The AMT is determined by calculating the actual execution time of the task under quiescent conditions and providing a time margin for taking into account variables that may cause the execution time to vary. To ensure that these critical tasks are carried out within their respective AMTs, throttle circuits are provided in control devices which can be set to limit the maximum speed of transfer of each device which effectively minimizes or blocks their utilization of the bus for given periods of time. An example of throttling is shown in the time graphs of
FIGS. 1B through 1E
. Referring to
FIG. 1A
, suppose task
2
is the critical task of a control device. Time line
10
exemplifies a time when task
2
would normally complete its execution, the time interval
12
represents the time margin and time line
14
represents the time when task
2
must be completed so as not to exceed its AMT.
FIG. 1B
depicts an example where a DMA controller which is performing another task requires access of the bus at the time task
2
is being performed. The bus arbiter, then, would have to regulate the access to the bus. If the throttling time of the DMA controller is set too short, it will gain access to the bus frequently causing the execution of task
2
to exceed its AMT by a substantial amount of time as shown in FIG.
1
B. In
FIG. 1C
, the throttle time of the DMA controller is increased, but still inadequate to permit the completion of task
2
within its AMT and the same happens in the example of FIG.
1
D. Finally, in the example of
FIG. 1E
, the throttle time of the DMA controller is set to permit task
2
to end within its AMT (see line
14
of FIG.
1
A), but the setting is too coarse, not allowing for another DMA cycle to be performed until well into task
3
which may affect the margin established for the task being performed by the DMA controller.
Accordingly, a throttling circuit programmable with fine throttling time resolutions (as close as possible to the processor clock period) to permit a maximizing of task execution while maintaining the margins of other control devices concurrently utilizing the processor's shared resources is desirable. This fine tuning is especially desirable in real time applications in which critical software tasks are abundant.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence; an arbiter circuit for regulating access of said control devices to the system resource; and a throttle circuit corresponding to each control device, each throttle circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.
In accordance with another aspect of the present invention, a throttle circuit is operative for use in each of a plurality of control devices of a processing system which comprises a shared system resource; and an arbiter circuit for regulating access of the control devices to the system resource, each control device assignable with a task having a predetermined maximum time to complete, the control devices time sharing the system resource in the process of performing their assigned tasks in accordance with a predetermined sequence. The throttle circuit comprises a delay circuit coupled to the arbiter circuit and individually programmable to control in cooperation with the arbiter circuit utilization of the system resource by the corresponding control device so that each control device may perform its task within the predetermined maximum completion time thereof.
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James Robert Ward
Waldie Arthur Howard
Calfee Halter & Griswold LLP
Goodrich Corp.
King Justin I.
Percio David R.
Thai Xuan M.
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