Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2011-01-18
2011-01-18
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S034000
Reexamination Certificate
active
07872495
ABSTRACT:
A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.
REFERENCES:
patent: 7205788 (2007-04-01), Wang et al.
patent: 7692451 (2010-04-01), Ishikawa
patent: 7782647 (2010-08-01), Lee et al.
Hsieh Cheng H.
Marlett Mark J.
Tran Toan D.
Cho James
Webostad W. Eric
Xilinx , Inc.
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