Programmable state machine employing a cache-like arrangement

Details Programmable state machine employing a cache-like arrangement Programmable state machine employing a cache-like arrangement

1995-09-28

1999-05-18

An, Meng-Ai T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, G06F13/00

Patent

active

059059028

ABSTRACT:
The programmable state machine includes a tag entry array and a new state array. All permissible combinations of current states and input values are represented within the tag entry array. The corresponding new state, to be transitioned to for each combination of current states and input values, is stored in the new state array. The tag entry array receives the current state and the input signals and generates a hit signal identifying which of the tag entries corresponds to the current state and input value signals. The new state array outputs the corresponding new state, based upon the hit signal received. In one embodiment, the tag entry array is configured as a fully associative cache tag entry array. In another embodiment, the tag entry array is configured as a set associative cache array. To eliminate the need to redundantly store a single new state, that corresponds to a large number of different transitions, a compare under mask arrangement is provided. As an alternative, a default new state arrangement is provided which outputs a default new state if a miss is detected within the tag entry array.

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Intel, Cache Tutorial, Intel Corporation, 1991, pp. 1-1 to 1-4, 1991.

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