Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-04-24
2004-05-04
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S082000, C326S046000, C327S210000
Reexamination Certificate
active
06731137
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits, and more specifically to digital logic input/output terminal circuits for interfacing programmable logic devices with other integrated circuit devices.
2. Description of the Related Art
A programmable logic device (“PLD”) is an integrated circuit adapted to permit a user to establish an arbitrary logic circuit of his own. A PLD includes primarily a configurable programmable logic element (“PLE”) for constructing a user's own logic, a memory cell for defining a circuit function, and multiple programmable input/output (“I/O”) circuits for each of its externally accessible I/O pins. The programmable I/O circuits can be used to input electronic signals to and output electronic signals from PLDs and/or integrated circuit devices in a variety of types of electronic systems. For example, the programmable I/O circuits may be used to interface multiple PLDs through a bi-directional bus so that they may communicate with each other.
Each I/O pin connected to the bi-directional bus always remains in a valid state provided there is a driver imposing a defined logic state on the bi-directional bus. However, when all 3-state output bus drivers connected to the bi-directional bus are in an inactive, high-impedance state, a voltage determined by the leakage currents of the components connected to the bi-directional bus develops giving rise to an entirely undefined voltage level at the I/O pins. An I/O pin having an undefined voltage level is known as a floating I/O pin. Allowing I/O pins to float can result in increased power consumption caused by the leakage currents from affected components and/or excessive noise due to unwanted oscillatory outputs. Increased power consumption or voltage oscillation can cause damage to all components connected to the bi-directional bus and disturb the electronic system. Therefore, all I/O pins should be held at a valid logic state when they are not being used, or when the output driver circuit driving them is placed in a high-impedance state.
In many instances, bus hold and/or weak pull-up circuits are used to resolve floating I/O pin problems.
FIG. 1
shows a conventional implementation of a bus hold and weak pull-up circuit (“conventional bus hold and weak pull-up circuit”)
100
used in a PLD programmable I/O circuit. The conventional bus hold and weak pull-up circuit
100
includes a weak pull-up circuit
105
, a bus hold circuit
110
, an inverter
150
, and a switch transistor (switch)
115
. The weak pull-up circuit
105
is connected to a first node of the switch
115
and the bus hold circuit
110
is connected to a second node of the switch
115
. The bus hold circuit
110
includes a first resistor
140
, a first CMOS inverter
125
, a second CMOS inverter
130
, and a second resistor
145
connected back to back forming a latch. The weak enable circuit
105
is a p-channel transistor. The switch transistor
115
is also a p-channel transistor. The input of inverter
150
is connected to the gate of the switch transistor
115
and the output of the inverter
150
is connected to the weak enable circuit
105
. The first resistor
140
is 8.5 K Ohms and the second resistor
145
is 7.5 K Ohms. The conventional bus hold and weak pull-up circuit
100
can be programmed to enable or disable the weak pull-up circuit
105
when the PLD is in programming mode. Furthermore, the conventional bus hold and weak pull-up circuit
100
can be programmed to operate in weak pull-up mode, bus hold mode, or neither when the PMD is in user operating mode.
The conventional bus hold and weak pull-up circuit
100
was designed to provide both the ‘last state’ hold feature and the resistor pull-up feature to eliminate the occurrence of floating I/O pins without glitches when operating in user operating mode. However, the conventional bus hold and weak pull-up circuit
100
does not eliminate the occurrence of floating I/O pins when the PLD transitions from programing mode to user operating mode. For instance, PLD I/O pins may float for a period of time as the conventional bus hold and weak pull-up circuit
100
transitions from programming mode with the weak pull-up feature enabled to user operating mode with the bus hold feature enabled. In another instance, PLD I/O pins may float for a period of time as the conventional bus hold and weak pull-up circuit
100
transitions from programming mode to user operating mode where the weak pull-up feature is disabled in programming mode and the bus hold feature is enabled in user operating mode. Examples of these two instances are given below.
FIG. 2
shows a timing diagram illustrating the operation of the conventional bus hold and weak pull-up circuit
100
when transitioning from the weak pull-up feature in programming mode to the bus hold feature in user operating mode. The PLD is in programming mode from time t
0
until time t
2
. The PLD switches to user operating mode at time t
2
. At time t
0
the bus hold enable signal ({overscore (EN)}
2
) is at a logical high state, the switch enable signal ({overscore (EN)}
1
) is at a logical high state, and the weak pull-up enable signal ({overscore (EN)}
1
) is at a logical low state. A logical high state can herein be referred to as high and a logical low state can herein be referred to as low. When {overscore (EN)}
2
is high, the first inverter
125
and the second inverter
130
are both disabled, thus the bus hold feature is disabled. When EN
1
is high, the switch
105
is open disconnecting the bus hold circuit
110
from the weak pull-up circuit
105
and the I/O pin
120
. Node
135
, which represents the bus hold value (BH-VAL) floats when the bus hold circuit
110
is disabled, or when the bus hold circuit is disconnected from the I/O pin
120
and weak pull-up circuit
105
. Therefore, node
135
floats at time t
0
. When {overscore (EN)}
1
is low, the weak pull-up circuit
105
is enabled. The weak pull-up circuit
105
pulls-up the I/O pin
120
to a defined logic state (e.g. VCC) to prevent the I/O pin
120
from floating. Accordingly, the weak pull-up circuit
105
pulls-up the I/O pin
120
to a logical high state at time t
0
.
At time t
1
the first CMOS inverter
125
and the second CMOS inverter
130
are enabled when {overscore (EN)}
2
transitions from a high to a low. Since the node
135
remains floating at time t
1
the outputs of the first and second CMOS inverters
125
and
130
also remain floating. However, since CMOS inverters generally have a defined state at their output, the outputs of the CMOS inverters
125
and
130
eventually settle to either a logical high or a logical low after a period of time. Whether the outputs of the first and second CMOS inverters
125
and
130
settle to a high or a low is not known until the outputs of the first and second CMOS inverters
125
and
130
are actually measured. For purposes of this example, the output of the second CMOS inverter
130
settles to a low. Therefore, node
135
also settles to a low. Note that at time t
1
the weak pull-up circuit
105
remains enabled, thus the I/O pin
120
remains high.
At time t
2
the PLD transitions from programming mode to user operating mode when EN
1
transitions from a high to a low and {overscore (EN)}
1
transitions from a low to a high. This event disables the weak pull-up circuit
105
and closes the switch
115
placing the logical state at node
135
(a logical low) in contention with the logical state at the I/O pin
120
(a logical high). This contention causes the I/O pin
120
to toggle or float for a period of time before the logical high node
135
forces the I/O pin
120
to a logical low at time t
3
. This result is undesirable to users who are expecting the I/O pin
120
to remain at a logical high at time t
2
when the PLD transitions from programming to user operating mode. As stated above, allowing I/O pins to float can result in increased power consumption caused by the leakage currents from affected components and/or excessi
Chang Tzung-Chin
Chong Yan
Huang Joseph
Kim In Whan
Nguyen Khai
Altera Corporation
Chang Daniel D.
Morrison & Foerster
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