Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Reexamination Certificate
2001-03-15
2004-08-31
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Accelerating charge or discharge
C365S233100
Reexamination Certificate
active
06785180
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to a programmable soft-start control for a charge pump in a semiconductor-integrated circuit.
Flash memory cards have a range of voltage requirements in order to drive the integral flash-memory devices, controllers, and analog circuits. A charge pump is a typical power-supply circuit that is capable of providing for these voltage requirements through voltage conversion.
In systems that use flash memory cards, as such a card is hot-plugged, it is desirable to extend the time period to fully power the card in order to control the high inrush or surge current at turn on. If the current is not controlled, damage may be done to the card's connectors and components. Additionally, the power supply circuit breaker may also trip resulting in a shutdown of the whole system. Accordingly, a soft-start is performed by controlling the ramp-up rate of the applied voltage(s) in order to provide a relatively constant current to the card's load capacitance while it is charging. Inrush current limiting is also beneficial because dv/dt control reduces both the EMI due to current and voltage spikes, and the stress on capacitors and the semiconductor devices surrounding the circuitry.
For flash memory cards, embedded charge pumps provide several amps to an array of flash memory devices and typically control the voltage ramp-up rate with a timing capacitor. However, because these circuits use timing capacitors, such circuits lack the ability to adjust for finer soft-start control and the ability to quickly program specific soft-start settings according to desired pump turn-on conditions.
Therefore, there is a need for a programmable soft-start control in a charge pump circuit that allows for finer soft-start control via firmware and that adds flexibility to applying specific soft-start settings according to charge pump turn-on conditions.
SUMMARY OF THE INVENTION
The above-mentioned need is met by providing a programmable soft-start control for a charge pump according to the present invention. Clocked pulse-frequency modulation (PFM) is used to control the charge and discharge phase. The soft-start control provides digital logic which breaks up the hard voltage ramp-up of the charge pump's output voltage into a series of discrete voltage ramp-up steps. Preferably, the soft start control provides a charging-series of seven voltage ramp-up rate steps, in which the frequency of these steps can be preprogrammed via an 8-bit register. Since the charge pump is turned on at least in two conditions, during initial powering or flash programming, each of the two registers can be programmed to provide a desired frequency of the charging-series of voltage ramp-up rate steps for one of the two conditions. Detection logic is provided to detect which of the two conditions is present and thus, the soft-start control automatically switches over to the proper pre-programmed frequency for the charging-series of voltage ramp-up rate steps.
In one embodiment of the present invention, provided is a programmable soft-start control for a charge pump. The charge pump provides a voltage output, a charge-off signal output when the voltage output is below a target voltage, charge-strength selector inputs which set a voltage ramp-up rate of the voltage output by controlling the strength of the charging transistor, a clock input (PCLK) which controls the charge and discharge phase, and a PUMPON signal input which controls the turn on of the pump circuit. The soft-start control comprises a charging-series circuit coupled to the charge-off signal output and the charge-strength selector inputs of the charge pump. The charging-series circuit is adapted to provide a charging-series output to the charge-strength selector inputs. The soft start control further includes at least one frequency selector circuit providing a clock pulse output that is used by the charging-series circuit for a specific soft-start condition of the charge pump. The at least one frequency selector circuit can be programmed to select a frequency of the clock pulse output.
In another embodiment of the present invention, provided is a method for controlling a voltage ramp-up rate of a charge pump providing an output voltage under specific soft-start conditions, the charge pump having charge-strength selector inputs which in conjunction with a PFM clock input set a voltage ramp-up rate of the output voltage. The method comprises programming at least one memory register to set both a divisor for a divide-by-n counter/prescaler and a clock signal input for a specific soft-start condition of the charge pump, and producing a clock signal pulse of a specific frequency based on digital logic stored in the at least one memory register. The method further includes driving a charging-series output with the clock signal pulse at the specific frequency, and providing the charging-series output to the charge-strength selector inputs of the charge pump to vary the voltage ramp-up rate of the output voltage of the charge pump for each of the specific soft-start condition.
In still another embodiment of the present invention, provided is a programmable soft-start control for use with an external circuit. The soft-start control comprises a pair of frequency selector circuits each having programmable non-volatile memory, a multiplexer adapted to receive clock signal inputs from the external circuit and having selection inputs and a selected output, a counter having data inputs for setting a frequency of a clock pulse output, and a gate circuit. Each of the data inputs of the counter and each of the selection inputs of the multiplexer are coupled to a separate bit register of the memory. The selected output of the multiplexer is coupled both to a clock input of the counter and a clock input of the gate. A charging-series circuit includes a bit counter providing a series of outputs. The soft-start control further comprises a detection and selection circuit having a multiplexer and a flip-flop circuit. The multiplexer is coupled to the gate of each of the pair of frequency selector circuits such that the multiplexer provides the clock pulse output of the counter to clock the bit counter of the charging-series circuit. The flip-flop sets which one of the pair of frequency selector circuits provides the clock pulse output to the charging-series circuit based on input from the external circuit.
In yet another embodiment of the present invention, provided is an apparatus comprising a flash memory, and a charge pump. The charge pump provides a voltage output to the flash memory, a charge-off signal output when the voltage output is below a target voltage for at least two specific operating conditions of the charge pump, and charge-strength selector inputs which set a voltage ramp-up rate of the voltage output. The apparatus further comprises a soft-start control coupled to the charge-strength selector inputs of the charge pump and providing a binary series output. The binary series output results in the voltage output of the charge pump reaching the target voltage in a time period having a series of voltage ramp-up rate steps. The soft-start control includes a counter producing the binary series output, a programmable memory register for each of the at least two specific operating conditions of the charge pump and which selects a frequency of the binary series output, and a detection and selection circuit. The detection and selection circuit is adapted to detect the specific operating condition of the charge pump and select the correct the binary series output for the specific operating condition when the detection and selection circuit and the counter receive the charge-off signal output from the charge pump.
In yet another embodiment of the present invention, provided is a host system comprising a system bus for communicating information through the host system, a voltage supply providing voltage over the system bus, a processor for processing instructions coupled to th
Dinsmore & Shohl LLP
Le Thong
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