Programmable signal termination for FPGAs and the like

Details Programmable signal termination for FPGAs and the like Programmable signal termination for FPGAs and the like

2005-08-02

2005-08-02

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S083000, C326S086000, C326S090000, C327S108000

Reexamination Certificate

active

06924659

ABSTRACT:
A termination scheme for the I/O circuitry of a programmable device, such as a field-programmable gate array (FPGA), has programmable resistors switchably connected between reference voltages and two of the device's I/O pads and additional programmable resistors switchably connected between the two I/O pads. By appropriately controlling the reference voltages and the resistance levels, a single implementation of the termination scheme can be used to conform to a relatively wide variety of symmetric and non-symmetric complementary and differential signaling applications.

REFERENCES:
patent: 6452420 (2002-09-01), Wong
patent: 6480026 (2002-11-01), Andrews et al.
patent: 6683472 (2004-01-01), Best et al.
U.S. Appl. No. 10/397,669, filed Mar. 26, 2003, Rahman et al.
“Multi-Drop LVDS with Virtex-E FPGAs”. By Jon Burnetti and Brian Von Herzen, Xilinx XAPP231, Version 1.0, Sep. 23, 1999, pp. 1-11.

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