Static information storage and retrieval – Read/write circuit – Signals
Patent
1997-10-17
2000-06-06
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Signals
36518909, 36518905, G11C 700
Patent
active
060727330
ABSTRACT:
A programmable sense amplifier delay (PSAD) circuit that is matched to the response of the memory array due to temperature and voltage supply Vcc. The circuit includes an inverter, a pull-up transistor, a pull-down transistor of the type of the cells of the memory array and a plurality of capacitors. The inverter responds to a predetermined voltage drop between the voltage level of the voltage source and the voltage on the input line. The pull-up transistor is connected between the voltage source Vcc and the input line and is activatable during a pre-charge phase of the memory array to raise the voltage level of the input line towards the voltage source. The pull-down transistor is connected between the input line and a ground source and is activatable after the pre-charge phase to discharge the voltage level of the input line. The capacitors are selectively connected in parallel to the pull-down transistor and define the speed at which the pull-down transistor discharges the input line. The invention also incorporates the voltage drop inverter.
REFERENCES:
patent: 4894561 (1990-01-01), Nogami
patent: 5424985 (1995-06-01), McClure et al.
patent: 5638333 (1997-06-01), Lee
Le Vu A.
Waferscale Integration Inc.
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