Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-10-27
2001-10-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S046000, C326S041000
Reexamination Certificate
active
06304100
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a programmable gate array capable of determining a function by externally applied data.
2. Description of the Background Art
In the electronic industry, it is becoming increasingly important that new products are developed in a shorter period of time. The increase in the function level and reduction in the size of the new products are essential to the development of the semiconductor device with an integrated circuit. Therefore, a semiconductor device which can be developed in a shorter period of time is desirable.
Recently, a FPGA (Field Programmable Gate Array) has become of major interest as a semiconductor device which can be developed in a short period of time. The FPGA is a semiconductor device which performs a prescribed operation as supplied in a preliminary provided internal circuit with data by a user.
Conventionally, an ASIC (Application Specific Integrated Circuit) such as a standard cell or gate array has generally been used to develop a large scale integration in a short period of time. However, in the ASIC, a mask must be changed to change the function and, a prescribed manufacturing process must be performed using the changed mask. Namely, with the ASIC, the function cannot be changed without a service of a semiconductor manufacturer. Therefore, there has been a need for a semiconductor device capable of more flexibly coping with the change. Recently, the FPGA can be provided with a large scale circuit and more often used for reducing the development period of the new products.
The FPGA includes a plurality of circuit blocks arranged in an array, around which interconnection regions are provided. Each circuit block is provided with a programmable element, the state of which determining a function of the circuit block. The programmable elements are also provided in the interconnection regions, the state of the programmable element determining a relation between the circuit blocks.
As the programmable element, a fuse, antifuse or the like is used, or a combination of a switching element and a volatile RAM or a non-volatile memory holding setting data controlling the switching element is used. In the case of the volatile RAM, the setting data is lost once the power is turned off, so that an ROM (Read Only Memory), PROM (Programmable ROM) or the like for holding the setting data is externally connected to the FPGA. Thus, every time the power is turned on, the setting data is transferred to the volatile RAM in the FPGA.
On the other hand, with the recent increase in the integration degree of the semiconductor devices, design properties are on sale as IPs (Intellectual Properties), which are data including circuit information, by a variety of IP vendors. Some IP vendors write their own IPs in the FPGAs for providing them to the user, so that the user can customize the portion other than the IP in the FPGA for use in accordance with a system. In most cases, the IP vendors desire that the setting data for the IP which is set in the FPGA should not be accessed by the user.
However, in the conventional FPGA, the setting data for the IP has disadvantageously been accessed by the user.
For example, for the FPGA externally provided with the ROM, another FPGA having the same function can readily be produced by copying a content stored in the ROM. In addition, data is transferred from the ROM to the FPGA through an interconnection when the power is turned on. As the interconnection can readily be probed, the setting data for the IP may disadvantageously be accessed.
On the other hand, for the FPGA internally provided with a non-volatile memory, data can be read or displayed by a hardware for a program as in the PROM for verification of a design specification or analyzing the operation. Namely, when the hardware for the program suited to the specification of the FPGA is used, the setting data including circuit information can readily be read and a FPGA having the same function is disadvantageously produced.
Therefore, recently even in some types of the FPGAs internally provided with the non-volatile memory, once the setting data including circuit information is written, the circuit information is protected against writing and reading, so that a copy thereof is not created.
In the FPGA, however, any additional setting data cannot be written by the user for providing a circuit for connection to its own system after the IP vendor writes the setting data for the IP so as to prevent access to the circuit information.
The scale of logic circuits which can be incorporated in the FPGA has been on the increase. Provision of several IPs on the scale of a microprocessor has become possible to form a system LSI (Large Scale Integration) with a FPGA of one chip. However, if the IPs of a single FPGA are provided by a plurality of vendors, it is difficult to write a plurality of IPs to the same FPGA while preventing unauthorized copying of the IPs.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a programmable gate array which can be provided with a plurality of IPs in a single chip while ensuring security of an IP vendor.
In short, the present invention relates to a semiconductor device provided with first and second circuit regions. The first and second circuit regions have functions of performing logical operations in accordance with setting data when the setting data is externally applied. The first circuit region is used for a first data provider in which a first function is determined when the first data is applied and which maintains the first function. The second circuit region is used for a second data provider in which a second function is determined when the second data is applied and which maintains the second function.
According to another aspect of the present invention, a programmable semiconductor device is provided which has a plurality of circuit regions. The plurality of circuit regions are arranged in an array. Each circuit region has a function of performing a logical operation in accordance with setting data when the setting data is externally applied. Each circuit region has a non-volatile data holding circuit and a functional circuit performing the logical operation. The non-volatile data holding circuit holds rewritable setting data. The non-volatile holding circuit is initially in a writable state, and brought into a write inhibit state when a write inhibit selection signal is applied after application of the setting data. The functional circuit performs a logical operation in accordance with the setting data held by the non-volatile data holding circuit. The write inhibit selection signal can independently be applied to each of the plurality of circuit regions.
Therefore, a main advantage of the present invention is that the user can use a user circuit and an IP circuit in a single chip and the access to circuit information by the user is prevented, so that reduction in the size of the system and power consumption can be achieved.
Another advantage of the present invention is that a region used for the IP is arbitrarily selected from a plurality of basic circuit regions and a first circuit (a circuit which is used for the first time) data is written, whereby a floor plan with high performance can be implemented which enables efficient use of the basic circuit region.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4933898 (1990-06-01), Gilberg et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5349249 (1994-09-01), Chiang et al.
patent: 5367207 (1994-11-01), Goetting et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5801547 (1998-09-01), Kean
patent: 5828229 (1998-10-01), Cliff et al.
patent: 2-232960 (1990-09-01), None
patent: 4-114449 (1992-04-01), None
patent: 5-267457 (1993-10
Chang Daniel D.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tokar Michael
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