Programmable scheduler for digital signal processor

Details Programmable scheduler for digital signal processor Programmable scheduler for digital signal processor

2006-09-19

2006-09-19

Bullock, Jr., Lewis A. (Department: 2195)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S264000, C710S260000, C710S266000, C712S035000, C712S229000, C718S103000

Reexamination Certificate

active

07111089

ABSTRACT:
A digital signal processor operates in conjunction with a scheduler hardware module and a scheduler software module in executing a highest priority runnable event among a plurality of events. The scheduler hardware module communicates an interrupt request signal to the DSP that is indicative of any change in a highest priority runnable event. The scheduler software module is executed by the DSP in response to the interrupt request signal indicating a change in highest priority runnable event. An execution of the scheduler software module by the DSP implements one of a various modes of an interrupt request routine.

REFERENCES:
patent: 4964000 (1990-10-01), Kanota et al.
patent: 5303369 (1994-04-01), Borcherding et al.
patent: 5465335 (1995-11-01), Anderson
patent: 5577250 (1996-11-01), Anderson et al.
patent: 5768613 (1998-06-01), Asghar
patent: 5832262 (1998-11-01), Johnson et al.
patent: 5937199 (1999-08-01), Temple
patent: 6006320 (1999-12-01), Parady
patent: 6108744 (2000-08-01), Lebee
patent: 6230255 (2001-05-01), Asghar et al.
patent: 6567910 (2003-05-01), Tessarolo et al.
patent: 6633940 (2003-10-01), Alasti et al.
patent: 6915517 (2005-07-01), Imamura et al.
patent: 6986066 (2006-01-01), Morrow et al.
patent: 7020879 (2006-03-01), Nemirovsky et al.
patent: 2002/0073129 (2002-06-01), Wang et al.
patent: 2003/0120702 (2003-06-01), Jahnke
patent: 465054 (1992-01-01), None
Lui Sha, Ragunathan Rajkumar, John P. Lhoczky, “Priority Inheritance Protocols: An Approach to Real-Time Synchronization”, IEEE Transactions on Computers, vol. 29, No. 9, Sep. 1990, pp. 1175-1185.
Jia Xu, David Lorge Parnas, “Scheduling Processes with Release Times, Deadlines, Precedence, and Exclusion Relations”, IEEE Transactions on Software Engineering, vol. 16, No. 3, Mar. 1990, pp. 360-369.

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