Programmable routing structures providing shorter timing...

Details Programmable routing structures providing shorter timing... Programmable routing structures providing shorter timing...

2006-11-14

2006-11-14

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S037000, C326S038000, C326S039000, C326S040000, C326S047000, C326S101000

Reexamination Certificate

active

07135888

ABSTRACT:
Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

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“APEX 20K Programmable Logic Device Family,” Data Sheet version 2.06 from Altera Corporation San Jose, CA (Mar. 2000).
“MAX 7000 Programmable Logic Device Family,” Data Sheet version 8.01 from Altera Corporation San Jose, CA (Jul. 1999).

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