Programmable ROM and parity programmable ROM having a correction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

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Details

714773, 714763, 714764, 714767, 714768, 714769, G11C 2900, G06F 1100

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active

060528168

ABSTRACT:
A semiconductor storage unit includes: a first PROM; a second PROM for storing parity data based on data stored in the first PROM; an error detecting circuit for detecting an error in read data outputted from the first PROM on the basis of the parity data outputted from the second PROM to generate an error detection signal; an error correcting circuit for outputting the data read out from the first PROM as it is when no error detection signal is supplied thereto, and for outputting error corrected data when the error detection signal is supplied thereto; a specific-mode detecting circuit for generating a specific-mode detection signal when detecting a specific mode; and a different-data generating means for generating data different from data outputted from the error correcting circuit as output data when both of the error detection signal and the specific-mode detection signal are generated.

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Michael David Quinn et al., "Dynamic Testing of Memory Arrays Which Utilize Error Checking and Correction (ECC) Logic", Digest of Paper 1980 IEEE Test Conference, Sep. 1980, pp. 238-252.

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