Programmable refresh scheduler for embedded DRAMs

Details Programmable refresh scheduler for embedded DRAMs Programmable refresh scheduler for embedded DRAMs

2005-05-24

2005-05-24

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S222000, C365S230030, C365S230060, C365S230080, C365S189040, C713S400000, C713S500000

Reexamination Certificate

active

06898663

ABSTRACT:
In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.

REFERENCES:
patent: 5742554 (1998-04-01), Fujioka
patent: 5959923 (1999-09-01), Matteson et al.
patent: 5970507 (1999-10-01), Kato et al.
patent: 6307776 (2001-10-01), So et al.
patent: 6415353 (2002-07-01), Leung
patent: 6472922 (2002-10-01), Paluch et al.

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