Programmable refresh scheduler for embedded DRAMs

Details Programmable refresh scheduler for embedded DRAMs Programmable refresh scheduler for embedded DRAMs

2001-08-14

2003-10-14

Sparks, Donald (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S222000, C365S230030, C365S230060, C365S230080, C365S189040

Reexamination Certificate

active

06633952

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to dynamic random access memories (DRAMs). More specifically, the invention relates to a programmable refresh scheduler for embedded DRAMs.
BACKGROUND OF THE INVENTION
RAM devices have become widely accepted in the semiconductor industry. Furthermore, system-on-chip (SOC) devices typically include internal RAM for storage of information such as instructions and/or data. Internal memory blocks in an SOC device typically occupy substantial chip area of an integrated circuit (IC) chip that contains the SOC device. For example, internal memory blocks may occupy as much as about 70% of the IC chip area of an SOC device. The configuration of internal memory in SOC devices are generally similar to the configuration of memory in individual memory chips.
Each block of RAM includes a number of memory cells. Each memory cell typically stores one bit of information. Typical RAM blocks have capacity to store anywhere from thousands to millions of bits of data. Since vast numbers of memory cells are used to store information in RAM blocks, the size of RAM blocks depends, to large extent, on the size of each memory cell.
Memory cells in dynamic random access memory (DRAM) blocks typically require less number of transistors per bit than cells in a static random access memory (SRAM). DRAMs typically cost less to produce than other types of memory devices due to their relative simplicity. For example, some DRAM blocks contain memory cells with three transistor (3-T) per bit, while other DRAM blocks contain memory cells with one transistor (1-T) per bit. Therefore, DRAM blocks of SOC devices and DRAM chips are typically smaller than SRAM blocks with similar information storage capacity.
However, DRAM cells need to be refreshed periodically for retaining the stored charge. A typical refresh operation comprises of selecting a memory cell, reading the stored value, and writing the same stored value back to the respective cell. Since typically the memory is accessed one word at-a-time, the refresh operation may be performed at a higher rate of one word at-a-time rather than one cell at-a-time, however, the time interval between refreshing word may still be large. This large time interval between refreshing particular words may not be sufficient for memory cells in a large memory module to retain their charges.
The maximum time interval between required refreshes is directly proportional to the capacitance of the DRAM cell and exponentially related to the (additive) inverse of the absolute operating temperature. Traditional DRAM memories are fabricated with a capacitance of 15-30 femto-Farad per bit. This capacitance is achieved by chip fabrication steps which are not usually a part of logic CMOS processing. DRAM memories which are integrated on-chip and fabricated with a standard CMOS process flow have a lower capacitance, in the range of 3-10femto-Farad per bit for 0.18 um technology. These cells require shorter refresh intervals. For a large memory, it may be necessary to refresh more than one memory word simultaneously to meet the refresh interval requirement, particularly at temperatures above 100 C.
Furthermore, traditional mechanisms for selecting a word of a hierarchical memory for refresh involves supplying an address that is decoded and results in the unique activation of a memory bank and one global word line. This mechanism utilizes almost the entire memory infrastructure to accomplish an action that is local to a particular memory block.
Therefore, there is a need for a flexible system and method capable of refreshing many words simultaneously.
SUMMARY OF THE INVENTION
Present invention describes a new design that allows for efficient refreshing of DRAMs. In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple banks and a programmable multiple memory rows in each bank simultaneously.
In one aspect, the present invention describes a DRAM programmable for simultaneous refreshing of a plurality of memory words comprising: a plurality of memory banks each memory bank including a plurality of memory blocks and each memory block including a plurality of memory words; a plurality of bank decoders for selecting a respective memory bank; a plurality of word decoders for selecting a respective memory word in a memory block; a plurality of local sense amplifiers for amplifying data for a plurality of local bit lines respectively; and a programmable register for selecting a plurality of memory words for simultaneous refreshing.
The programmable register may be programed to simultaneously refresh a plurality of memory words in a selected plurality of memory banks, or to simultaneously refresh a plurality of memory words in a selected memory bank. Furthermore, a second register may be programed to simultaneously refresh a plurality of memory words in each selected memory bank, while the first register is programed to simultaneously refresh a plurality of memory words in a selected plurality of memory banks.
In another aspect, the present invention discloses a method for simultaneously refreshing a plurality of DRAM words, the method comprising the steps of: arranging the DRAM with a plurality of memory banks, each memory bank including a plurality of memory blocks, wherein each memory bank is selectable by a bank decoder; arranging each memory block with a plurality of memory words, wherein each memory word is selectable by a word decoder; and programming a register for selecting a plurality of memory words to be refreshed simultaneously.


REFERENCES:
patent: 5742554 (1998-04-01), Fujioka
patent: 5959923 (1999-09-01), Matteson et al.
patent: 5970507 (1999-10-01), Kato et al.
patent: 6307776 (2001-10-01), So et al.
patent: 6415353 (2002-07-01), Leung

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