Programmable redundancy scheme suitable for single-bit state and

Details Programmable redundancy scheme suitable for single-bit state and Programmable redundancy scheme suitable for single-bit state and

1994-06-02

1995-08-01

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365 49, 36518902, 36518907, G11C 700

Patent

active

054385466

ABSTRACT:
A nonvolatile memory includes a first and a second output, a main array having a first and a second column, and a redundant array having a first and a second redundant column. A logic includes a first and a second CAM set. The first CAM set activates the first redundant column to replace the first column if defective. The second CAM set activates the second redundant column to replace the second column if it is defective. A configuration circuit is provided for controlling the logic to selectively couple the first and second columns and the first and second redundant columns to the first and second outputs. When the configuration circuit is in a first state, the logic couples the first redundant column to the first output if it is activated and the second redundant column to the second output if it is activated. When the configuration circuit is in a second state, the logic couples (1) the first redundant column to the first and second outputs when the first column is defective and addressed, (2) the second column to the first and second outputs when the second column is addressed and the first column is defective, or (3) the second redundant column to the first and second outputs when the second column is addressed and defective.

REFERENCES:
patent: 4376300 (1983-03-01), Tsang
patent: 4601019 (1986-07-01), Shah et al.
patent: 4807191 (1989-02-01), Flannagan
patent: 5031142 (1991-07-01), Castro
patent: 5065364 (1991-11-01), Atwood et al.
patent: 5083294 (1992-01-01), Okajima
patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5327383 (1994-07-01), Merchant et al.
patent: 5347484 (1994-09-01), Kwong et al.
B. F. Fitzgerald et al., "Memory System with High-Performance Word Redundancy," IBM Technical Disclosure Bulletin, vol. 19, No. 5, pp. 1638-1639 (Oct. 1976).

Affiliated with

Also associated with

Rating

Programmable redundancy scheme suitable for single-bit state and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable redundancy scheme suitable for single-bit state and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable redundancy scheme suitable for single-bit state and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-738161