Programmable read/write access signal and method therefor

Details Programmable read/write access signal and method therefor Programmable read/write access signal and method therefor

1996-04-01

1999-02-16

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395310, 711100, 711111, G06F 1338

Patent

active

058729402

ABSTRACT:
A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory devices. A chip select register value 604, 608, 612 is preprogrammed with respect to each external device coupled to the processor (101). This preprogrammed register value 604, 608, 612 is used by the system bus controller (103) to uniquely configure a read/write access signal to be sent to each of the external devices (111, 112, 113).

REFERENCES:
patent: 4933845 (1990-06-01), Hayes
patent: 5265243 (1993-11-01), Povenmire et al.
patent: 5408129 (1995-04-01), Farmwald et al.
patent: 5444852 (1995-08-01), Nakabayashi
patent: 5448744 (1995-09-01), Eifert et al.
patent: 5535349 (1996-07-01), Boaz et al.
patent: 5557757 (1996-09-01), Gephardt et al.
patent: 5590287 (1996-12-01), Zeller et al.

Affiliated with

Also associated with

Rating

Programmable read/write access signal and method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable read/write access signal and method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable read/write access signal and method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2069995