Programmable read only memory with high speed differential...

Details Programmable read only memory with high speed differential... Programmable read only memory with high speed differential...

2000-01-04

2001-01-09

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185180, C365S185200

Reexamination Certificate

active

06172923

ABSTRACT:

TECHNICAL FIELD
The present claimed invention relates to the field of semiconductor devices. Specifically, the present claimed invention relates to an apparatus and a method for storing and retrieving non-volatile read only memory.
BACKGROUND ART
Read only memory (ROM) is a vital component of modern computers. Beneficially, ROM is a non-volatile memory and, theoretically, can maintain the data it stores indefinitely without power. ROM data is configured in an array of memory cells, each of which has the capability of generating a binary digit. A binary digit is either a logic ‘1’ (high voltage level) or a logic ‘0’ (low voltage level). The basic component of a memory cell is a transistor and hence will be referred to as a memory cell transistor.
As mentioned, read only memory (ROM) is comprised of an array of memory cell transistors, each of which has the capability of generating a binary digit. A ROM circuit is formed by arranging a plurality of memory cell transistors into a matrix (rows and columns). Typically, two sets of 8 transistors are grouped in each row to create two ‘bytes’, or one ‘word’, of information for a given row. The gates of all the transistors in each row are connected to a horizontal conductor line referred to as a ‘word line.’ The purpose of the word line is to turn on the gates of all transistors grouped in that word line. Hence, the top word line, coupling sixteen memory cell transistors, is referred to as word line 0, the second word line, linking sixteen different memory cell transistors, is referred to as word line 1, and so on. An x-decoder interprets an input address code to determine the appropriate word-line to which the address refers and then enables that word line.
For a NOR logic arrangement of transistors, the memory cell transistors in a vertical column are either uncoupled from a vertical metal line called a bitline or are coupled in parallel to each other to the bitline. A separate bitline exists for each vertical column of memory cell transistors. For example, sixteen bitlines exist for a word of bits (e.g. 16 binary digits or memory cell transistors in a row). The bitline communicates the actual logic level of the memory cell transistors to other portions of the ROM circuit. A y-decoder interprets an input address code to determine the appropriate bitline to which the address refers and then enables that bitline. With this grid of horizontal and vertical metal lines, each memory cell transistor, and its logic level, can be accessed by enabling the appropriate word line and appropriate bitline to which the desired memory cell transistor is coupled.
Prior Art
FIG. 1
illustrates a pair of conventional memory cell transistors within a ROM circuit
100
. Memory cell transistor
102
represents a logic level ‘0’ as its drain
103
couples bitline
104
to ground
190
. When gate
116
of memory cell transistor
102
is enabled by word line
114
, to which it is coupled, its source
118
, is coupled to ground
190
via its drain
103
. Thus, when bitline
104
is precharged, its voltage level will go to ground because of the coupling just described.
Conversely, memory cell transistor
106
represents a logic level ‘1’ as its drain
107
is uncoupled from bitline
108
. When gate
112
of memory cell transistor
106
is enabled by word line
114
, to which it is coupled, its source
110
, coupled to ground
190
, is thereby coupled to ground
190
via its drain
107
. Thus, when bitline
108
is precharged, its voltage level will remain at the voltage level of the precharge because of the coupling arrangement just described.
However, the difference in the typical configuration of the memory cell transistors for logic level 0 and logic level 1 state in the prior art creates a problem. Because memory cell transistor
102
representing a logic level of 0 is coupled to the bitline
104
, its transistor body adds capacitance to the bitline in which it is grouped. Conversely, a memory cell transistor
106
representing a logic level of 1 has no portion of the memory cell transistor
106
coupled to bitline
108
. Hence it adds no capacitance to bitline
108
in which it is grouped.
Although the difference in capacitance of an individual memory cell transistor may be small, its effect is amplified in at least two circumstances. First, many transistors can be grouped in a single bitline and thus, the additive effect of their capacitance can be substantial. Second, bitlines may be polarized, e.g. have data memory transistors of all one state. Thus, for example, it is possible that all the data memory transistors in one bitline could have 0 logic (increasing the capacitive load on the bitline by the sum of the individual capacitance) while all the data memory transistors in another bitline could have 1 logic (adding no capacitive load to the bitline). With this polarized difference, a significant variation in bitline capacitive loading can occur within the ROM circuit.
Consequently, the variation of the capacitance in bitlines can create a corresponding variation in the precharging and subsequent voltage level and phase from one bitline to the next. As a result of this drawback in the prior art, a need exists in a ROM circuit for a data memory transistor that has an approximately equivalent capacitive loading on the bitline in both the logic 0 state and the logic 1 state.
Prior Art
FIG. 2
illustrates a conventional precharge and sensing circuit
200
for conventional ROM memory. Memory cell
202
represents a single memory cell transistor, as discussed above for
FIG. 1
, as enabled by its corresponding word line
114
and bitline
104
. Reference cell
204
has a logic level that will be compared against the logic level of memory cell
202
following a precharge step. PMOS pull-up transistor
206
, coupled to power supply voltage
208
, supplies a precharge voltage level to memory cell
202
while PMOS pull-up transistor
210
, coupled to power supply voltage
212
, supplies a voltage level to reference cell
204
.
However, NMOS pull-up transistor
214
, coupled to power supply
216
, and NMOS pull-up transistor
218
, coupled to power supply
220
, prevent memory cell
202
and reference cell
204
respectively, from achieving a precharge voltage level equivalent to that of power supply
208
and
212
. Assuming all power supply voltages
208
,
212
,
216
, and
218
are equivalent, NMOS pull-up transistor
214
and
218
and NMOS bias transistors
222
and
224
, for memory cell
202
and reference cell
204
respectively, require a voltage at the source electrode of the transistor to be less than or equal to the gate voltage minus the characteristic threshold voltage of the NMOS transistor.
In other words, memory cell
202
and reference cell
204
cannot be charged to a voltage level equivalent to the voltage level equivalent to that of power supply
208
,
212
,
216
, and
218
. Rather, memory cell
202
and reference cell
204
can only be charged to a voltage level equivalent to the voltage level of power supply
208
,
212
,
216
, and
218
minus the threshold voltage level of the NMOS transistors. This prevents the circuit from operating at a power supply voltage level that is less than minimum high logic voltage level plus the threshold voltage. Consequently, a need exists for a precharge circuit with the capability to provide an improved voltage level to memory cell
202
and reference cell
204
when power supply
208
,
212
,
215
and
220
are at a low-voltage condition.
Additionally, the conventional precharge circuit uses only a single PMOS pull-up transistor
206
and
210
to precharge the memory cell and reference cell respectively. The resultant speed at which the cells are precharged is subsequently limited by this configuration. The limitation subsequently slows down the entire memory retrieval process of ROM data. Consequently, a need exists for a precharge circuit that will precharge the cells in a faster manner.
As a final feature of the conventional precharge circuit, the PMOS pull-up transistor
206
and
210
indepe

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