Programmable queue structures for multiprocessors

Details Programmable queue structures for multiprocessors Programmable queue structures for multiprocessors

2010-05-10

2011-11-01

Tsai, Henry (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C711S146000

Reexamination Certificate

active

08051227

ABSTRACT:
A command is received from a first agent via a first predetermined memory-mapped register, the first agent being one of multiple agents representing software processes, each being executed by one of processor cores of a network processor in a network element. A first queue associated with the command is identified based on the first predetermined memory-mapped register. A pointer is atomically read from a first hardware-based queue state register associated with the first queue. Data is atomically accessed at a memory location of the memory based on the pointer. The pointer stored in the first hardware-based queue state register is atomically updated, including incrementing the pointer of the first hardware-based queue state register, reading a queue size of the queue from a first hardware-based configuration register associated with the first queue, and wrapping around the pointer if the pointer reaches an end of the first queue based on the queue size.

REFERENCES:
patent: 5375223 (1994-12-01), Meyers et al.
patent: 7225300 (2007-05-01), Choquette et al.
patent: 2004/0139305 (2004-07-01), Arimilli et al.
patent: 2004/0225765 (2004-11-01), Greer
patent: 2005/0160139 (2005-07-01), Boucher et al.

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