Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-03-02
2000-05-23
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
327170, 327172, 327175, 327176, 327291, G11C 2900, H03K 504, H03K 708
Patent
active
060676485
ABSTRACT:
A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.
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Hunter Paul R.
Lawrence Archer R.
Little Jack C.
Moise Emmanuel L.
Tanisys Technology, Inc.
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